mtd: rawnand: fsl_elbc: Cosmetic move
Move the fsl_elbc_attach_chip function after the definitions of fsl_elbc_read_page and friends in preparation for the next patch. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>hifive-unleashed-5.2
Marek Behún
Miquel Raynal
parent
7e8afca5cf
commit
9fed311591
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@ -635,79 +635,6 @@ static int fsl_elbc_wait(struct nand_chip *chip)
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return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
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}
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static int fsl_elbc_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_lbc_ctrl *ctrl = priv->ctrl;
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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unsigned int al;
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/* calculate FMR Address Length field */
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al = 0;
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if (chip->pagemask & 0xffff0000)
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al++;
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if (chip->pagemask & 0xff000000)
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al++;
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priv->fmr |= al << FMR_AL_SHIFT;
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dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
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nanddev_ntargets(&chip->base));
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dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
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nanddev_target_size(&chip->base));
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dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
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chip->pagemask);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
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chip->legacy.chip_delay);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
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chip->badblockpos);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
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chip->chip_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
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chip->page_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
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chip->phys_erase_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
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chip->ecc.mode);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
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chip->ecc.steps);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
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chip->ecc.bytes);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
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chip->ecc.total);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n",
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mtd->ooblayout);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
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mtd->erasesize);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
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mtd->writesize);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
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mtd->oobsize);
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/* adjust Option Register and ECC to match Flash page size */
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if (mtd->writesize == 512) {
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priv->page_size = 0;
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clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
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} else if (mtd->writesize == 2048) {
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priv->page_size = 1;
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setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
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} else {
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dev_err(priv->dev,
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"fsl_elbc_init: page size %d is not supported\n",
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mtd->writesize);
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return -ENOTSUPP;
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}
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return 0;
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}
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static const struct nand_controller_ops fsl_elbc_controller_ops = {
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.attach_chip = fsl_elbc_attach_chip,
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};
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static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf,
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int oob_required, int page)
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{
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@ -815,6 +742,79 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
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return 0;
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}
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static int fsl_elbc_attach_chip(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_lbc_ctrl *ctrl = priv->ctrl;
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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unsigned int al;
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/* calculate FMR Address Length field */
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al = 0;
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if (chip->pagemask & 0xffff0000)
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al++;
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if (chip->pagemask & 0xff000000)
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al++;
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priv->fmr |= al << FMR_AL_SHIFT;
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dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
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nanddev_ntargets(&chip->base));
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dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
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nanddev_target_size(&chip->base));
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dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
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chip->pagemask);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
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chip->legacy.chip_delay);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
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chip->badblockpos);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
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chip->chip_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
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chip->page_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
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chip->phys_erase_shift);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
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chip->ecc.mode);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
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chip->ecc.steps);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
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chip->ecc.bytes);
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dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
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chip->ecc.total);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n",
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mtd->ooblayout);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
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mtd->erasesize);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
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mtd->writesize);
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dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
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mtd->oobsize);
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/* adjust Option Register and ECC to match Flash page size */
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if (mtd->writesize == 512) {
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priv->page_size = 0;
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clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
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} else if (mtd->writesize == 2048) {
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priv->page_size = 1;
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setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
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} else {
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dev_err(priv->dev,
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"fsl_elbc_init: page size %d is not supported\n",
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mtd->writesize);
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return -ENOTSUPP;
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}
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return 0;
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}
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static const struct nand_controller_ops fsl_elbc_controller_ops = {
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.attach_chip = fsl_elbc_attach_chip,
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};
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static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
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{
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
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