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drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12 

Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
alistair/sunxi64-5.4-dsi
Xiaojie Yuan 2019-05-16 20:01:03 +08:00 committed by Alex Deucher
parent 716e9bb099
commit 9ff3dba6d6
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -1228,6 +1228,7 @@ static int gfx_v10_0_sw_init(void *handle)
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 1;