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ARM: shmobile: r8a73a4: add Z2 clock support

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The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC.
Add a definition for this clock to later use it from the arm_big_little
CPUFreq driver.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Guennadi Liakhovetski 2013-06-21 09:10:38 +02:00 committed by Simon Horman
parent d1c3c959f2
commit a040f22d2c
1 changed files with 17 additions and 0 deletions
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17
arch/arm/mach-shmobile/clock-r8a73a4.c
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@ -323,6 +323,21 @@ static struct clk z_clk = {
.ops = &zclk_ops,
};
/*
* It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
* switching is only available in auto-DVFS mode
*/
SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
static struct clk z2_clk = {
.parent = &pll0_div2_clk,
.div_mask = 0x1f,
.enable_bit = 0,
/* We'll need to access FRQCRB and FRQCRC */
.enable_reg = (void __iomem *)FRQCRB,
.ops = &zclk_ops,
};
static struct clk *main_clks[] = {
&extalr_clk,
&extal1_clk,
@ -341,6 +356,8 @@ static struct clk *main_clks[] = {
&pll2s_clk,
&pll2h_clk,
&z_clk,
&pll0_div2_clk,
&z2_clk,
};
/* DIV4 */