drm/nouveau/clk/gk20a: put mnp values into their own struct
This allows us to read them using one single function and will be handy to the GM20B driver. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -115,23 +115,29 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
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.min_pl = 1, .max_pl = 32,
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};
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struct gk20a_pll {
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u32 m;
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u32 n;
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u32 pl;
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};
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struct gk20a_clk {
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struct nvkm_clk base;
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const struct gk20a_clk_pllg_params *params;
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u32 m, n, pl;
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struct gk20a_pll pll;
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u32 parent_rate;
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};
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static void
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gk20a_pllg_read_mnp(struct gk20a_clk *clk)
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gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 val;
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val = nvkm_rd32(device, GPCPLL_COEFF);
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clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
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clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
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pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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}
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static u32
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@ -140,8 +146,8 @@ gk20a_pllg_calc_rate(struct gk20a_clk *clk)
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u32 rate;
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u32 divider;
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rate = clk->parent_rate * clk->n;
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divider = clk->m * pl_to_div[clk->pl];
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rate = clk->parent_rate * clk->pll.n;
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divider = clk->pll.m * pl_to_div[clk->pll.pl];
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return rate / divider / 2;
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}
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@ -256,16 +262,16 @@ found_match:
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"no best match for target @ %dMHz on gpc_pll",
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target_clk_f / KHZ);
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clk->m = best_m;
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clk->n = best_n;
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clk->pl = best_pl;
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clk->pll.m = best_m;
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clk->pll.n = best_n;
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clk->pll.pl = best_pl;
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target_freq = gk20a_pllg_calc_rate(clk);
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nvkm_debug(subdev,
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"actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
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target_freq / MHZ, clk->m, clk->n, clk->pl,
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pl_to_div[clk->pl]);
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target_freq / MHZ, clk->pll.m, clk->pll.n, clk->pll.pl,
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pl_to_div[clk->pll.pl]);
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return 0;
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}
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@ -352,25 +358,24 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 val, cfg;
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u32 m_old, pl_old, n_lo;
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struct gk20a_pll old_pll;
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u32 n_lo;
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/* get old coefficients */
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val = nvkm_rd32(device, GPCPLL_COEFF);
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m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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gk20a_pllg_read_mnp(clk, &old_pll);
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/* do NDIV slide if there is no change in M and PL */
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cfg = nvkm_rd32(device, GPCPLL_CFG);
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if (allow_slide && clk->m == m_old && clk->pl == pl_old &&
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(cfg & GPCPLL_CFG_ENABLE)) {
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return gk20a_pllg_slide(clk, clk->n);
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if (allow_slide && clk->pll.m == old_pll.m &&
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clk->pll.pl == old_pll.pl && (cfg & GPCPLL_CFG_ENABLE)) {
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return gk20a_pllg_slide(clk, clk->pll.n);
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}
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/* slide down to NDIV_LO */
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if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
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int ret;
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n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco,
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n_lo = DIV_ROUND_UP(old_pll.m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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ret = gk20a_pllg_slide(clk, n_lo);
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@ -400,13 +405,13 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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gk20a_pllg_disable(clk);
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nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
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clk->m, clk->n, clk->pl);
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clk->pll.m, clk->pll.n, clk->pll.pl);
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n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco,
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n_lo = DIV_ROUND_UP(clk->pll.m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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val = clk->m << GPCPLL_COEFF_M_SHIFT;
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val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT;
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val |= clk->pl << GPCPLL_COEFF_P_SHIFT;
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val = clk->pll.m << GPCPLL_COEFF_M_SHIFT;
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val |= (allow_slide ? n_lo : clk->pll.n) << GPCPLL_COEFF_N_SHIFT;
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val |= clk->pll.pl << GPCPLL_COEFF_P_SHIFT;
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nvkm_wr32(device, GPCPLL_COEFF, val);
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gk20a_pllg_enable(clk);
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@ -441,7 +446,7 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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}
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/* slide up to new NDIV */
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return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0;
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return allow_slide ? gk20a_pllg_slide(clk, clk->pll.n) : 0;
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}
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static int
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@ -563,7 +568,7 @@ gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
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case nv_clk_src_crystal:
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return device->crystal;
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case nv_clk_src_gpc:
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gk20a_pllg_read_mnp(clk);
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gk20a_pllg_read_mnp(clk, &clk->pll);
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return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
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default:
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nvkm_error(subdev, "invalid clock source %d\n", src);
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@ -603,11 +608,11 @@ gk20a_clk_fini(struct nvkm_clk *base)
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/* slide to VCO min */
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val = nvkm_rd32(device, GPCPLL_CFG);
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if (val & GPCPLL_CFG_ENABLE) {
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u32 coef, m, n_lo;
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struct gk20a_pll pll;
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u32 n_lo;
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coef = nvkm_rd32(device, GPCPLL_COEFF);
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m = (coef >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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n_lo = DIV_ROUND_UP(m * clk->params->min_vco,
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gk20a_pllg_read_mnp(clk, &pll);
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n_lo = DIV_ROUND_UP(pll.m * clk->params->min_vco,
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clk->parent_rate / KHZ);
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gk20a_pllg_slide(clk, n_lo);
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}
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