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MIPS: mscc: ocelot: add MIIM1 bus 

There is an additional MIIM (MDIO) bus in this SoC so let's declare it
in the dtsi.

This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
support for internal PHY reset on this bus on the contrary of MIIM0 so
there is only one register address space and not two.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20014/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
hifive-unleashed-5.1
Quentin Schulz 2018-07-25 14:22:41 +02:00 committed by Paul Burton
parent 49e5bb13ad
commit a0553e01f8
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GPG Key ID: 3EA79FACB57500DD
1 changed files with 16 additions and 0 deletions
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16
arch/mips/boot/dts/mscc/ocelot.dtsi
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@ -178,6 +178,11 @@
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
miim1: miim1 {
pins = "GPIO_14", "GPIO_15";
function = "miim1";
};
};
mdio0: mdio@107009c {
@ -201,5 +206,16 @@
reg = <3>;
};
};
mdio1: mdio@10700c0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mscc,ocelot-miim";
reg = <0x10700c0 0x24>;
interrupts = <15>;
pinctrl-names = "default";
pinctrl-0 = <&miim1>;
status = "disabled";
};
};
};