ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs
To ensure correct alignment of cacheline-aligned data, the maximum cacheline size needs to be known at compile time. Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely that there will be future ARMv7 implementations with the same line size) then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline size. For CPUs with smaller caches, this will result in some harmless padding but will help with single zImage work and avoid hitting subtle bugs with misaligned data structures. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -825,7 +825,6 @@ config ARCH_S5PC100
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select HAVE_CLK
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select CLKDEV_LOOKUP
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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select ARCH_USES_GETTIMEOFFSET
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C_RTC if RTC_CLASS
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@ -842,7 +841,6 @@ config ARCH_S5PV210
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select HAVE_CLK
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select ARM_L1_CACHE_SHIFT_6
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select ARCH_HAS_CPUFREQ
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select GENERIC_CLOCKEVENTS
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select HAVE_SCHED_CLOCK
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@ -15,7 +15,6 @@ config ARCH_MX53
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config SOC_IMX50
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bool
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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select MXC_TZIC
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select ARCH_MXC_IOMUX_V3
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select ARCH_MXC_AUDMUX_V2
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@ -25,7 +24,6 @@ config SOC_IMX50
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config SOC_IMX51
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bool
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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select MXC_TZIC
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select ARCH_MXC_IOMUX_V3
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select ARCH_MXC_AUDMUX_V2
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@ -35,7 +33,6 @@ config SOC_IMX51
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config SOC_IMX53
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bool
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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select MXC_TZIC
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select ARCH_MXC_IOMUX_V3
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select ARCH_MX53
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@ -33,7 +33,6 @@ config ARCH_OMAP3
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default y
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select CPU_V7
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select USB_ARCH_HAS_EHCI
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select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
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select ARCH_HAS_OPP
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select PM_OPP if PM
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select ARM_CPU_SUSPEND if PM
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@ -882,6 +882,7 @@ config CACHE_XSC3L2
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config ARM_L1_CACHE_SHIFT_6
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bool
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default y if CPU_V7
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help
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Setting ARM L1 cache line size to 64 Bytes.
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