drm/i915/guc: Make scratch register base and count flexible
We are using some scratch registers in MMIO based send function. Make their base and count flexible in preparation of upcoming GuC firmware/hardware changes. While around, change cmd len parameter verification from WARN_ON to GEM_BUG_ON as we don't need this all the time. v2: call out WARN/GEM_BUG change in the commit msg (Daniele) v3: don't overqualify the ints (Chris) v4: rebase and use proper enum Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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@ -260,9 +260,36 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
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__intel_uc_fw_fini(&dev_priv->huc.fw);
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__intel_uc_fw_fini(&dev_priv->huc.fw);
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}
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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GEM_BUG_ON(!guc->send_regs.count);
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GEM_BUG_ON(i >= guc->send_regs.count);
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return _MMIO(guc->send_regs.base + 4 * i);
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}
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static void guc_init_send_regs(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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enum forcewake_domains fw_domains = 0;
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unsigned int i;
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guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
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guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
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for (i = 0; i < guc->send_regs.count; i++) {
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fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
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guc_send_reg(guc, i),
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FW_REG_READ | FW_REG_WRITE);
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}
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guc->send_regs.fw_domains = fw_domains;
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}
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static int guc_enable_communication(struct intel_guc *guc)
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static int guc_enable_communication(struct intel_guc *guc)
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{
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{
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/* XXX: placeholder for alternate setup */
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/* XXX: placeholder for alternate setup */
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guc_init_send_regs(guc);
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guc->send = intel_guc_send_mmio;
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guc->send = intel_guc_send_mmio;
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return 0;
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return 0;
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}
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}
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@ -407,19 +434,19 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
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int i;
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int i;
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int ret;
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int ret;
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if (WARN_ON(len < 1 || len > 15))
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GEM_BUG_ON(!len);
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return -EINVAL;
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GEM_BUG_ON(len > guc->send_regs.count);
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mutex_lock(&guc->send_mutex);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
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intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
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dev_priv->guc.action_count += 1;
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dev_priv->guc.action_count += 1;
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dev_priv->guc.action_cmd = action[0];
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dev_priv->guc.action_cmd = action[0];
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for (i = 0; i < len; i++)
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for (i = 0; i < len; i++)
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I915_WRITE(SOFT_SCRATCH(i), action[i]);
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I915_WRITE(guc_send_reg(guc, i), action[i]);
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POSTING_READ(SOFT_SCRATCH(i - 1));
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POSTING_READ(guc_send_reg(guc, i - 1));
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intel_guc_notify(guc);
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intel_guc_notify(guc);
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@ -428,7 +455,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
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* Fast commands should still complete in 10us.
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* Fast commands should still complete in 10us.
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*/
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*/
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ret = __intel_wait_for_register_fw(dev_priv,
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ret = __intel_wait_for_register_fw(dev_priv,
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SOFT_SCRATCH(0),
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guc_send_reg(guc, 0),
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INTEL_GUC_RECV_MASK,
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INTEL_GUC_RECV_MASK,
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INTEL_GUC_RECV_MASK,
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INTEL_GUC_RECV_MASK,
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10, 10, &status);
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10, 10, &status);
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@ -450,7 +477,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
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}
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}
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dev_priv->guc.action_status = status;
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dev_priv->guc.action_status = status;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
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intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
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mutex_unlock(&guc->send_mutex);
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mutex_unlock(&guc->send_mutex);
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return ret;
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return ret;
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@ -205,6 +205,13 @@ struct intel_guc {
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uint64_t submissions[I915_NUM_ENGINES];
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uint64_t submissions[I915_NUM_ENGINES];
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uint32_t last_seqno[I915_NUM_ENGINES];
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uint32_t last_seqno[I915_NUM_ENGINES];
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/* GuC's FW specific registers used in MMIO send */
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struct {
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u32 base;
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unsigned int count;
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enum forcewake_domains fw_domains;
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} send_regs;
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/* To serialize the intel_guc_send actions */
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/* To serialize the intel_guc_send actions */
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struct mutex send_mutex;
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struct mutex send_mutex;
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