drm/i915: ValleyView mode setting limits and PLL functions
Add some VLV limit structures and update the PLL code. v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits v3: re-add dpio write function v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
cc889e0f6c
commit
a0c4da24ea
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@ -904,6 +904,7 @@
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#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
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#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
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#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
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#define DPLL_LOCK_VLV (1<<15)
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#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
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#define SRX_INDEX 0x3c4
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@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static bool
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intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static inline u32 /* units of 100MHz */
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intel_fdi_link_freq(struct drm_device *dev)
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{
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@ -359,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
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.find_pll = intel_find_pll_ironlake_dp,
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};
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static const intel_limit_t intel_limits_vlv_dac = {
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.dot = { .min = 25000, .max = 270000 },
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.vco = { .min = 4000000, .max = 6000000 },
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.n = { .min = 1, .max = 7 },
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.m = { .min = 22, .max = 450 }, /* guess */
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.m1 = { .min = 2, .max = 3 },
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.m2 = { .min = 11, .max = 156 },
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.p = { .min = 10, .max = 30 },
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.p1 = { .min = 2, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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static const intel_limit_t intel_limits_vlv_hdmi = {
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.dot = { .min = 20000, .max = 165000 },
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.vco = { .min = 5994000, .max = 4000000 },
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.n = { .min = 1, .max = 7 },
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.m = { .min = 60, .max = 300 }, /* guess */
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.m1 = { .min = 2, .max = 3 },
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.m2 = { .min = 11, .max = 156 },
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.p = { .min = 10, .max = 30 },
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.p1 = { .min = 2, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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static const intel_limit_t intel_limits_vlv_dp = {
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.dot = { .min = 162000, .max = 270000 },
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.vco = { .min = 5994000, .max = 4000000 },
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.n = { .min = 1, .max = 7 },
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.m = { .min = 60, .max = 300 }, /* guess */
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.m1 = { .min = 2, .max = 3 },
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.m2 = { .min = 11, .max = 156 },
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.p = { .min = 10, .max = 30 },
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.p1 = { .min = 2, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
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{
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unsigned long flags;
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@ -384,6 +431,28 @@ out_unlock:
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return val;
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}
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static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
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u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->dpio_lock, flags);
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if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
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DRM_ERROR("DPIO idle wait timed out\n");
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goto out_unlock;
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}
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I915_WRITE(DPIO_DATA, val);
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I915_WRITE(DPIO_REG, reg);
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I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
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DPIO_BYTE);
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if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
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DRM_ERROR("DPIO write wait timed out\n");
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out_unlock:
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spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
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}
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static void vlv_init_dpio(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -510,6 +579,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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limit = &intel_limits_pineview_lvds;
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else
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limit = &intel_limits_pineview_sdvo;
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} else if (IS_VALLEYVIEW(dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
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limit = &intel_limits_vlv_dac;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
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limit = &intel_limits_vlv_hdmi;
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else
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limit = &intel_limits_vlv_dp;
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} else if (!IS_GEN2(dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_i9xx_lvds;
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@ -783,6 +859,73 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
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memcpy(best_clock, &clock, sizeof(intel_clock_t));
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return true;
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}
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static bool
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intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
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u32 m, n, fastclk;
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u32 updrate, minupdate, fracbits, p;
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unsigned long bestppm, ppm, absppm;
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int dotclk, flag;
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dotclk = target * 1000;
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bestppm = 1000000;
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ppm = absppm = 0;
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fastclk = dotclk / (2*100);
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updrate = 0;
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minupdate = 19200;
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fracbits = 1;
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n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
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bestm1 = bestm2 = bestp1 = bestp2 = 0;
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/* based on hardware requirement, prefer smaller n to precision */
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for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
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updrate = refclk / n;
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for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
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for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
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if (p2 > 10)
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p2 = p2 - 1;
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p = p1 * p2;
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/* based on hardware requirement, prefer bigger m1,m2 values */
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for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
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m2 = (((2*(fastclk * p * n / m1 )) +
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refclk) / (2*refclk));
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m = m1 * m2;
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vco = updrate * m;
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if (vco >= limit->vco.min && vco < limit->vco.max) {
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ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
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absppm = (ppm > 0) ? ppm : (-ppm);
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if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
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bestppm = 0;
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flag = 1;
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}
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if (absppm < bestppm - 10) {
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bestppm = absppm;
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flag = 1;
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}
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if (flag) {
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bestn = n;
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bestm1 = m1;
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bestm2 = m2;
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bestp1 = p1;
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bestp2 = p2;
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flag = 0;
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}
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}
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}
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}
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}
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}
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best_clock->n = bestn;
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best_clock->m1 = bestm1;
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best_clock->m2 = bestm2;
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best_clock->p1 = bestp1;
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best_clock->p2 = bestp2;
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return true;
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}
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static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
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{
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@ -1293,7 +1436,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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u32 val;
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/* No really, not for ILK+ */
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BUG_ON(dev_priv->info->gen >= 5);
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BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
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/* PLL is protected by panel, make sure we can write it */
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if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
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@ -3672,13 +3815,37 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
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return display_bpc != bpc;
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}
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static int vlv_get_refclk(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk = 27000; /* for DP & HDMI */
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return 100000; /* only one validated so far */
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
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refclk = 96000;
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} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv))
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refclk = 100000;
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else
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refclk = 96000;
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} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
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refclk = 100000;
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}
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return refclk;
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}
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static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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if (IS_VALLEYVIEW(dev)) {
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refclk = vlv_get_refclk(crtc);
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} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
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refclk = dev_priv->lvds_ssc_freq * 1000;
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DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
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@ -3793,6 +3960,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
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I915_WRITE(LVDS, temp);
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}
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static void vlv_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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int refclk, int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 dpll, mdiv, pdiv;
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u32 bestn, bestm1, bestm2, bestp1, bestp2;
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bool is_hdmi;
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is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
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bestn = clock->n;
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bestm1 = clock->m1;
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bestm2 = clock->m2;
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bestp1 = clock->p1;
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bestp2 = clock->p2;
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/* Enable DPIO clock input */
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dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
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DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
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I915_WRITE(DPLL(pipe), dpll);
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POSTING_READ(DPLL(pipe));
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mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
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mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
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mdiv |= ((bestn << DPIO_N_SHIFT));
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mdiv |= (1 << DPIO_POST_DIV_SHIFT);
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mdiv |= (1 << DPIO_K_SHIFT);
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mdiv |= DPIO_ENABLE_CALIBRATION;
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intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
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intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
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pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
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(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
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(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
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intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
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intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
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dpll |= DPLL_VCO_ENABLE;
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I915_WRITE(DPLL(pipe), dpll);
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POSTING_READ(DPLL(pipe));
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if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
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DRM_ERROR("DPLL %d failed to lock\n", pipe);
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if (is_hdmi) {
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u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (temp > 1)
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temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
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else
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temp = 0;
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I915_WRITE(DPLL_MD(pipe), temp);
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POSTING_READ(DPLL_MD(pipe));
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}
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intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
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}
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static void i9xx_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -4050,6 +4283,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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if (IS_GEN2(dev))
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i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
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else if (IS_VALLEYVIEW(dev))
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vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
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refclk, num_connectors);
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else
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i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
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has_reduced_clock ? &reduced_clock : NULL,
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