[ARM] 4947/1: htc-egpio, a driver for GPIO/IRQ expanders with fixed input/output pins
implemented in CPLD chips on several HTC devices. The original driver was written by Kevin O'Connor, I have adapted it to use gpiolib and made the bus/register widths configurable. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Philipp Zabel
Russell King
parent
e6816f34e4
commit
a1635b8fe5
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@ -22,6 +22,14 @@ config MFD_ASIC3
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This driver supports the ASIC3 multifunction chip found on many
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PDAs (mainly iPAQ and HTC based ones)
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config HTC_EGPIO
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bool "HTC EGPIO support"
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depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB
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help
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This driver supports the CPLD egpio chip present on
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several HTC phones. It provides basic support for input
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pins, output pins, and irqs.
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endmenu
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menu "Multimedia Capabilities Port drivers"
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@ -5,6 +5,8 @@
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obj-$(CONFIG_MFD_SM501) += sm501.o
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obj-$(CONFIG_MFD_ASIC3) += asic3.o
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obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
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obj-$(CONFIG_MCP) += mcp-core.o
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obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
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obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
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@ -0,0 +1,440 @@
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/*
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* Support for the GPIO/IRQ expander chips present on several HTC phones.
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* These are implemented in CPLD chips present on the board.
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*
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* Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
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* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
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*
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* This file may be distributed under the terms of the GNU GPL license.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/mfd/htc-egpio.h>
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struct egpio_chip {
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int reg_start;
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int cached_values;
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unsigned long is_out;
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struct device *dev;
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struct gpio_chip chip;
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};
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struct egpio_info {
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spinlock_t lock;
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/* iomem info */
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void __iomem *base_addr;
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int bus_shift; /* byte shift */
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int reg_shift; /* bit shift */
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int reg_mask;
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/* irq info */
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int ack_register;
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int ack_write;
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u16 irqs_enabled;
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uint irq_start;
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int nirqs;
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uint chained_irq;
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/* egpio info */
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struct egpio_chip *chip;
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int nchips;
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};
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static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
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{
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writew(value, ei->base_addr + (reg << ei->bus_shift));
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}
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static inline u16 egpio_readw(struct egpio_info *ei, int reg)
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{
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return readw(ei->base_addr + (reg << ei->bus_shift));
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}
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/*
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* IRQs
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*/
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static inline void ack_irqs(struct egpio_info *ei)
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{
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egpio_writew(ei->ack_write, ei, ei->ack_register);
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pr_debug("EGPIO ack - write %x to base+%x\n",
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ei->ack_write, ei->ack_register << ei->bus_shift);
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}
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static void egpio_ack(unsigned int irq)
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{
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}
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/* There does not appear to be a way to proactively mask interrupts
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* on the egpio chip itself. So, we simply ignore interrupts that
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* aren't desired. */
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static void egpio_mask(unsigned int irq)
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{
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struct egpio_info *ei = get_irq_chip_data(irq);
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ei->irqs_enabled &= ~(1 << (irq - ei->irq_start));
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pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled);
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}
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static void egpio_unmask(unsigned int irq)
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{
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struct egpio_info *ei = get_irq_chip_data(irq);
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ei->irqs_enabled |= 1 << (irq - ei->irq_start);
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pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled);
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}
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static struct irq_chip egpio_muxed_chip = {
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.name = "htc-egpio",
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.ack = egpio_ack,
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.mask = egpio_mask,
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.unmask = egpio_unmask,
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};
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static void egpio_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct egpio_info *ei = get_irq_data(irq);
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int irqpin;
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/* Read current pins. */
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unsigned long readval = egpio_readw(ei, ei->ack_register);
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pr_debug("IRQ reg: %x\n", (unsigned int)readval);
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/* Ack/unmask interrupts. */
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ack_irqs(ei);
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/* Process all set pins. */
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readval &= ei->irqs_enabled;
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for_each_bit(irqpin, &readval, ei->nirqs) {
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/* Run irq handler */
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pr_debug("got IRQ %d\n", irqpin);
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irq = ei->irq_start + irqpin;
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desc = &irq_desc[irq];
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desc->handle_irq(irq, desc);
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}
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}
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int htc_egpio_get_wakeup_irq(struct device *dev)
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{
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struct egpio_info *ei = dev_get_drvdata(dev);
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/* Read current pins. */
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u16 readval = egpio_readw(ei, ei->ack_register);
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/* Ack/unmask interrupts. */
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ack_irqs(ei);
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/* Return first set pin. */
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readval &= ei->irqs_enabled;
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return ei->irq_start + ffs(readval) - 1;
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}
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EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
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static inline int egpio_pos(struct egpio_info *ei, int bit)
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{
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return bit >> ei->reg_shift;
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}
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static inline int egpio_bit(struct egpio_info *ei, int bit)
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{
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return 1 << (bit & ((1 << ei->reg_shift)-1));
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}
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/*
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* Input pins
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*/
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static int egpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct egpio_chip *egpio;
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struct egpio_info *ei;
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unsigned bit;
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int reg;
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int value;
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pr_debug("egpio_get_value(%d)\n", chip->base + offset);
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egpio = container_of(chip, struct egpio_chip, chip);
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ei = dev_get_drvdata(egpio->dev);
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bit = egpio_bit(ei, offset);
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reg = egpio->reg_start + egpio_pos(ei, offset);
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value = egpio_readw(ei, reg);
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pr_debug("readw(%p + %x) = %x\n",
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ei->base_addr, reg << ei->bus_shift, value);
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return value & bit;
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}
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static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct egpio_chip *egpio;
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egpio = container_of(chip, struct egpio_chip, chip);
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return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
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}
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/*
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* Output pins
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*/
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static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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unsigned long flag;
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struct egpio_chip *egpio;
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struct egpio_info *ei;
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unsigned bit;
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int pos;
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int reg;
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int shift;
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pr_debug("egpio_set(%s, %d(%d), %d)\n",
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chip->label, offset, offset+chip->base, value);
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egpio = container_of(chip, struct egpio_chip, chip);
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ei = dev_get_drvdata(egpio->dev);
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bit = egpio_bit(ei, offset);
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pos = egpio_pos(ei, offset);
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reg = egpio->reg_start + pos;
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shift = pos << ei->reg_shift;
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pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
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reg, (egpio->cached_values >> shift) & ei->reg_mask);
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spin_lock_irqsave(&ei->lock, flag);
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if (value)
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egpio->cached_values |= (1 << offset);
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else
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egpio->cached_values &= ~(1 << offset);
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egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
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spin_unlock_irqrestore(&ei->lock, flag);
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}
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static int egpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct egpio_chip *egpio;
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egpio = container_of(chip, struct egpio_chip, chip);
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if (test_bit(offset, &egpio->is_out)) {
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egpio_set(chip, offset, value);
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return 0;
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} else {
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return -EINVAL;
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}
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}
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static void egpio_write_cache(struct egpio_info *ei)
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{
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int i;
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struct egpio_chip *egpio;
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int shift;
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for (i = 0; i < ei->nchips; i++) {
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egpio = &(ei->chip[i]);
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if (!egpio->is_out)
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continue;
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for (shift = 0; shift < egpio->chip.ngpio;
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shift += (1<<ei->reg_shift)) {
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int reg = egpio->reg_start + egpio_pos(ei, shift);
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if (!((egpio->is_out >> shift) & ei->reg_mask))
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continue;
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pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
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(egpio->cached_values >> shift) & ei->reg_mask,
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egpio_readw(ei, reg));
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egpio_writew((egpio->cached_values >> shift)
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& ei->reg_mask, ei, reg);
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}
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}
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}
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/*
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* Setup
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*/
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static int __init egpio_probe(struct platform_device *pdev)
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{
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struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
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struct resource *res;
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struct egpio_info *ei;
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struct gpio_chip *chip;
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unsigned int irq, irq_end;
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int i;
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int ret;
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/* Initialize ei data structure. */
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ei = kzalloc(sizeof(*ei), GFP_KERNEL);
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if (!ei)
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return -ENOMEM;
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spin_lock_init(&ei->lock);
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/* Find chained irq */
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ret = -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (res)
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ei->chained_irq = res->start;
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/* Map egpio chip into virtual address space. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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goto fail;
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ei->base_addr = ioremap_nocache(res->start, res->end - res->start);
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if (!ei->base_addr)
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goto fail;
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pr_debug("EGPIO phys=%08x virt=%p\n", res->start, ei->base_addr);
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if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
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goto fail;
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ei->bus_shift = fls(pdata->bus_width - 1) - 3;
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pr_debug("bus_shift = %d\n", ei->bus_shift);
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if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
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goto fail;
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ei->reg_shift = fls(pdata->reg_width - 1);
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pr_debug("reg_shift = %d\n", ei->reg_shift);
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ei->reg_mask = (1 << pdata->reg_width) - 1;
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platform_set_drvdata(pdev, ei);
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ei->nchips = pdata->num_chips;
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ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
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if (!ei) {
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ret = -ENOMEM;
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goto fail;
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}
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for (i = 0; i < ei->nchips; i++) {
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ei->chip[i].reg_start = pdata->chip[i].reg_start;
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ei->chip[i].cached_values = pdata->chip[i].initial_values;
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ei->chip[i].is_out = pdata->chip[i].direction;
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ei->chip[i].dev = &(pdev->dev);
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chip = &(ei->chip[i].chip);
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chip->label = "htc-egpio";
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chip->get = egpio_get;
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chip->set = egpio_set;
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chip->direction_input = egpio_direction_input;
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chip->direction_output = egpio_direction_output;
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chip->base = pdata->chip[i].gpio_base;
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chip->ngpio = pdata->chip[i].num_gpios;
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gpiochip_add(chip);
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}
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/* Set initial pin values */
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egpio_write_cache(ei);
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ei->irq_start = pdata->irq_base;
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ei->nirqs = pdata->num_irqs;
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ei->ack_register = pdata->ack_register;
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if (ei->chained_irq) {
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/* Setup irq handlers */
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ei->ack_write = 0xFFFF;
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if (pdata->invert_acks)
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ei->ack_write = 0;
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irq_end = ei->irq_start + ei->nirqs;
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for (irq = ei->irq_start; irq < irq_end; irq++) {
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set_irq_chip(irq, &egpio_muxed_chip);
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set_irq_chip_data(irq, ei);
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set_irq_handler(irq, handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
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set_irq_data(ei->chained_irq, ei);
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set_irq_chained_handler(ei->chained_irq, egpio_handler);
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ack_irqs(ei);
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device_init_wakeup(&pdev->dev, 1);
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}
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return 0;
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fail:
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printk(KERN_ERR "EGPIO failed to setup\n");
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kfree(ei);
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return ret;
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}
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static int __exit egpio_remove(struct platform_device *pdev)
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{
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struct egpio_info *ei = platform_get_drvdata(pdev);
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unsigned int irq, irq_end;
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if (ei->chained_irq) {
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irq_end = ei->irq_start + ei->nirqs;
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for (irq = ei->irq_start; irq < irq_end; irq++) {
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set_irq_chip(irq, NULL);
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set_irq_handler(irq, NULL);
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set_irq_flags(irq, 0);
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}
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set_irq_chained_handler(ei->chained_irq, NULL);
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device_init_wakeup(&pdev->dev, 0);
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}
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iounmap(ei->base_addr);
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kfree(ei->chip);
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kfree(ei);
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return 0;
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}
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#ifdef CONFIG_PM
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static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct egpio_info *ei = platform_get_drvdata(pdev);
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if (ei->chained_irq && device_may_wakeup(&pdev->dev))
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enable_irq_wake(ei->chained_irq);
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return 0;
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}
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static int egpio_resume(struct platform_device *pdev)
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{
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struct egpio_info *ei = platform_get_drvdata(pdev);
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if (ei->chained_irq && device_may_wakeup(&pdev->dev))
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disable_irq_wake(ei->chained_irq);
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/* Update registers from the cache, in case
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the CPLD was powered off during suspend */
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egpio_write_cache(ei);
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return 0;
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}
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#else
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#define egpio_suspend NULL
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#define egpio_resume NULL
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#endif
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static struct platform_driver egpio_driver = {
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.driver = {
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.name = "htc-egpio",
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},
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.remove = __exit_p(egpio_remove),
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.suspend = egpio_suspend,
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.resume = egpio_resume,
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};
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static int __init egpio_init(void)
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{
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return platform_driver_probe(&egpio_driver, egpio_probe);
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}
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static void __exit egpio_exit(void)
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{
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platform_driver_unregister(&egpio_driver);
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}
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/* start early for dependencies */
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subsys_initcall(egpio_init);
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module_exit(egpio_exit)
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");
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|
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@ -0,0 +1,57 @@
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/*
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* HTC simple EGPIO irq and gpio extender
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*/
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#ifndef __HTC_EGPIO_H__
|
||||
#define __HTC_EGPIO_H__
|
||||
|
||||
#include <linux/gpio.h>
|
||||
|
||||
/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
|
||||
#define HTC_EGPIO_OUTPUT (~0)
|
||||
#define HTC_EGPIO_INPUT 0
|
||||
|
||||
/**
|
||||
* struct htc_egpio_chip - descriptor to create gpio_chip for register range
|
||||
* @reg_start: index of first register
|
||||
* @gpio_base: gpio number of first pin in this register range
|
||||
* @num_gpios: number of gpios in this register range, max BITS_PER_LONG
|
||||
* (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
|
||||
* @direction: bitfield, '0' = input, '1' = output,
|
||||
*/
|
||||
struct htc_egpio_chip {
|
||||
int reg_start;
|
||||
int gpio_base;
|
||||
int num_gpios;
|
||||
unsigned long direction;
|
||||
unsigned long initial_values;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct htc_egpio_platform_data - description provided by the arch
|
||||
* @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
|
||||
* @num_irqs: number of irqs
|
||||
* @reg_width: number of bits per register, either 8 or 16 bit
|
||||
* @bus_width: alignment of the registers, either 16 or 32 bit
|
||||
* @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
|
||||
* @ack_register: location of the irq/ack register
|
||||
* @chip: pointer to array of htc_egpio_chip descriptors
|
||||
* @num_chips: number of egpio chip descriptors
|
||||
*/
|
||||
struct htc_egpio_platform_data {
|
||||
int bus_width;
|
||||
int reg_width;
|
||||
|
||||
int irq_base;
|
||||
int num_irqs;
|
||||
int invert_acks;
|
||||
int ack_register;
|
||||
|
||||
struct htc_egpio_chip *chip;
|
||||
int num_chips;
|
||||
};
|
||||
|
||||
/* Determine the wakeup irq, to be called during early resume */
|
||||
extern int htc_egpio_get_wakeup_irq(struct device *dev);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue