drm/i915: vebox interrupt get/put
v2: Use the correct lock to protect PM interrupt regs, this was accidentally lost from earlier (Haihao) Fix return types (Ben) Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1019,6 +1019,48 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
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gen6_gt_force_wake_put(dev_priv);
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}
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static bool
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hsw_vebox_get_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return false;
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spin_lock_irqsave(&dev_priv->rps.lock, flags);
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if (ring->irq_refcount.pm++ == 0) {
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u32 pm_imr = I915_READ(GEN6_PMIMR);
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I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
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I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
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POSTING_READ(GEN6_PMIMR);
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}
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spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
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return true;
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}
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static void
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hsw_vebox_put_irq(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long flags;
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if (!dev->irq_enabled)
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return;
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spin_lock_irqsave(&dev_priv->rps.lock, flags);
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if (--ring->irq_refcount.pm == 0) {
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u32 pm_imr = I915_READ(GEN6_PMIMR);
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I915_WRITE_IMR(ring, ~0);
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I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
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POSTING_READ(GEN6_PMIMR);
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}
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spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
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}
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static int
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i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 length,
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@ -1928,8 +1970,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
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ring->get_seqno = gen6_ring_get_seqno;
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ring->set_seqno = ring_set_seqno;
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ring->irq_enable_mask = 0;
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ring->irq_get = NULL;
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ring->irq_put = NULL;
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ring->irq_get = hsw_vebox_get_irq;
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ring->irq_put = hsw_vebox_put_irq;
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ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
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ring->sync_to = gen6_ring_sync;
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ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
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@ -73,8 +73,9 @@ struct intel_ring_buffer {
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u32 last_retired_head;
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struct {
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u32 gt;
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} irq_refcount; /* protected by dev_priv->irq_lock */
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u32 gt; /* protected by dev_priv->irq_lock */
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u32 pm; /* protected by dev_priv->rps.lock (sucks) */
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} irq_refcount;
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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u32 trace_irq_seqno;
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u32 sync_seqno[I915_NUM_RINGS-1];
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