Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next
Freescale updates from Scott: "Highlights include 8xx optimizations, 32-bit checksum optimizations, 86xx consolidation, e5500/e6500 cpu hotplug, more fman and other dt bits, and minor fixes/cleanup."hifive-unleashed-5.1
Michael Ellerman
commit
a1b5344620
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|
@ -315,6 +315,16 @@ PROPERTIES
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|||
Value type: <phandle>
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Definition: A phandle for 1EEE1588 timer.
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- pcsphy-handle
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Usage required for "fsl,fman-memac" MACs
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Value type: <phandle>
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||||
Definition: A phandle for pcsphy.
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- tbi-handle
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Usage required for "fsl,fman-dtsec" MACs
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Value type: <phandle>
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Definition: A phandle for tbiphy.
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EXAMPLE
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fman1_tx28: port@a8000 {
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@ -340,6 +350,7 @@ ethernet@e0000 {
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reg = <0xe0000 0x1000>;
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fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
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ptp-timer = <&ptp-timer>;
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tbi-handle = <&tbi0>;
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};
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============================================================================
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@ -415,6 +426,13 @@ PROPERTIES
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The settings and programming routines for internal/external
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MDIO are different. Must be included for internal MDIO.
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For internal PHY device on internal mdio bus, a PHY node should be created.
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See the definition of the PHY node in booting-without-of.txt for an
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example of how to define a PHY (Internal PHY has no interrupt line).
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- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
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- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
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PCS PHY addr must be '0'.
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EXAMPLE
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Example for FMan v2 external MDIO:
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@ -425,12 +443,29 @@ mdio@f1000 {
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interrupts = <101 2 0 0>;
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};
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Example for FMan v2 internal MDIO:
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mdio@e3120 {
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compatible = "fsl,fman-mdio";
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reg = <0xe3120 0xee0>;
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fsl,fman-internal-mdio;
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tbi1: tbi-phy@8 {
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reg = <0x8>;
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device_type = "tbi-phy";
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};
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};
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Example for FMan v3 internal MDIO:
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mdio@f1000 {
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compatible = "fsl,fman-memac-mdio";
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reg = <0xf1000 0x1000>;
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fsl,fman-internal-mdio;
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pcsphy6: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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=============================================================================
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@ -568,6 +603,7 @@ fman@400000 {
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cell-index = <0>;
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reg = <0xe0000 0x1000>;
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fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
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tbi-handle = <&tbi5>;
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};
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ethernet@e2000 {
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@ -575,6 +611,7 @@ fman@400000 {
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cell-index = <1>;
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reg = <0xe2000 0x1000>;
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fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
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tbi-handle = <&tbi6>;
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};
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ethernet@e4000 {
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@ -582,6 +619,7 @@ fman@400000 {
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cell-index = <2>;
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reg = <0xe4000 0x1000>;
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fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
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tbi-handle = <&tbi7>;
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};
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ethernet@e6000 {
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@ -589,6 +627,7 @@ fman@400000 {
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cell-index = <3>;
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reg = <0xe6000 0x1000>;
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fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
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tbi-handle = <&tbi8>;
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};
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ethernet@e8000 {
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@ -596,6 +635,7 @@ fman@400000 {
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cell-index = <4>;
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reg = <0xf0000 0x1000>;
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fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
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tbi-handle = <&tbi9>;
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ethernet@f0000 {
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cell-index = <8>;
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|
|
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@ -0,0 +1,63 @@
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* Run Control and Power Management
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-------------------------------------------
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The RCPM performs all device-level tasks associated with device run control
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and power management.
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Required properites:
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- reg : Offset and length of the register set of the RCPM block.
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- fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
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fsl,rcpm-wakeup property.
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- compatible : Must contain a chip-specific RCPM block compatible string
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and (if applicable) may contain a chassis-version RCPM compatible
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string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
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such as:
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* "fsl,p2041-rcpm"
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* "fsl,p5020-rcpm"
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* "fsl,t4240-rcpm"
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Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
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such as:
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* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
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* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
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* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
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All references to "1.0" and "2.0" refer to the QorIQ chassis version to
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which the chip complies.
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Chassis Version Example Chips
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--------------- -------------------------------
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1.0 p4080, p5020, p5040, p2041, p3041
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2.0 t4240, b4860, b4420
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2.1 t1040, ls1021
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Example:
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The RCPM node for T4240:
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rcpm: global-utilities@e2000 {
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compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
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reg = <0xe2000 0x1000>;
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fsl,#rcpm-wakeup-cells = <2>;
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};
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* Freescale RCPM Wakeup Source Device Tree Bindings
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-------------------------------------------
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Required fsl,rcpm-wakeup property should be added to a device node if the device
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can be used as a wakeup source.
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- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
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register cells. The number of IPPDEXPCR register cells is defined in
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"fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
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the bit mask that should be set in IPPDEXPCR0, and the second register
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cell is for IPPDEXPCR1, and so on.
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Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
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mechanism for keeping certain blocks awake during STANDBY and MEM, in
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order to use them as wake-up sources.
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Example:
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lpuart0: serial@2950000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2950000 0x0 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
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};
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@ -2582,7 +2582,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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nolapic_timer [X86-32,APIC] Do not use the local APIC timer.
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noltlbs [PPC] Do not use large page/tlb entries for kernel
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lowmem mapping on PPC40x.
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lowmem mapping on PPC40x and PPC8xx
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nomca [IA-64] Disable machine check abort handling
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|
|
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@ -408,7 +408,7 @@ config SWIOTLB
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config HOTPLUG_CPU
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bool "Support for enabling/disabling CPUs"
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depends on SMP && (PPC_PSERIES || \
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PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
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PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE)
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---help---
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Say Y here to be able to disable and re-enable individual
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CPUs at runtime on SMP machines.
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|
|
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|||
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@ -325,6 +325,16 @@ corenet64_smp_defconfig:
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$(call merge_into_defconfig,corenet_basic_defconfig,\
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85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw)
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PHONY += mpc86xx_defconfig
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mpc86xx_defconfig:
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$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
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86xx-hw fsl-emb-nonhw)
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PHONY += mpc86xx_smp_defconfig
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mpc86xx_smp_defconfig:
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$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
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86xx-smp 86xx-hw fsl-emb-nonhw)
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define archhelp
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@echo '* zImage - Build default images selected by kernel config'
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@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
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||||
|
|
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@ -1,7 +1,7 @@
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|||
/*
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||||
* B4860DS Device Tree Source
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||||
*
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||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
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|
@ -39,12 +39,69 @@
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model = "fsl,B4860QDS";
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compatible = "fsl,B4860QDS";
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aliases {
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phy_sgmii_1e = &phy_sgmii_1e;
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phy_sgmii_1f = &phy_sgmii_1f;
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phy_xaui_slot1 = &phy_xaui_slot1;
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phy_xaui_slot2 = &phy_xaui_slot2;
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};
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ifc: localbus@ffe124000 {
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board-control@3,0 {
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compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
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};
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};
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soc@ffe000000 {
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fman@400000 {
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ethernet@e8000 {
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phy-handle = <&phy_sgmii_1e>;
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phy-connection-type = "sgmii";
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};
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ethernet@ea000 {
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phy-handle = <&phy_sgmii_1f>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_xaui_slot1>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&phy_xaui_slot2>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
|
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phy_sgmii_1e: ethernet-phy@1e {
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reg = <0x1e>;
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status = "disabled";
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};
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phy_sgmii_1f: ethernet-phy@1f {
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reg = <0x1f>;
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status = "disabled";
|
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};
|
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};
|
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|
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mdio@fd000 {
|
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phy_xaui_slot1: xaui-phy@slot1 {
|
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compatible = "ethernet-phy-ieee802.3-c45";
|
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reg = <0x7>;
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status = "disabled";
|
||||
};
|
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|
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phy_xaui_slot2: xaui-phy@slot2 {
|
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compatible = "ethernet-phy-ieee802.3-c45";
|
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reg = <0x6>;
|
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status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
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reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
|
|
@ -55,7 +112,6 @@
|
|||
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "b4860si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 - 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -39,6 +39,13 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
phy_sgmii_10 = &phy_sgmii_10;
|
||||
phy_sgmii_11 = &phy_sgmii_11;
|
||||
phy_sgmii_1c = &phy_sgmii_1c;
|
||||
phy_sgmii_1d = &phy_sgmii_1d;
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
|
|
@ -135,7 +142,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
compatible = "sst,sst25wf040", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -210,6 +217,47 @@
|
|||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_10>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_11>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_1c>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy_sgmii_1d>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
phy_sgmii_10: ethernet-phy@10 {
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
phy_sgmii_11: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
phy_sgmii_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy_sgmii_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
|
|
@ -226,7 +274,6 @@
|
|||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* GE PPC9A Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
|
||||
*/
|
||||
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "GEF_PPC9A";
|
||||
compatible = "gef,ppc9a";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
lbc: localbus@fef05000 {
|
||||
reg = <0xfef05000 0x1000>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe8000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe0000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00008000 // FPGA
|
||||
5 0 0xfc008000 0x00008000 // AFIX FPGA
|
||||
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
|
||||
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,ppc9a-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,ppc9a-fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/* Second watchdog available, driver currently supports one.
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8 0x9 0 0>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@7,14000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
|
||||
reg = <0x7 0x14000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@fef00000 {
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
|
||||
i2c@3000 {
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@25000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
reg = <0xfef08000 0x1000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/*
|
||||
* GE SBC310 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
|
||||
*/
|
||||
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "GEF_SBC310";
|
||||
compatible = "gef,sbc310";
|
||||
|
||||
aliases {
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
lbc: localbus@fef05000 {
|
||||
reg = <0xfef05000 0x1000>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe0000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe8000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00010000>; // FPGA
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x01000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x01000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,sbc310-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/*
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8 0x9 0 0>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@4,8000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,sbc310-gpio";
|
||||
reg = <0x4 0x8000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@fef00000 {
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
|
||||
i2c@3000 {
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@25000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
reg = <0xfef08000 0x1000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@fef09000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfef09000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <0x19 0x2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xc0000000
|
||||
0x02000000 0x0 0xc0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* GE SBC610 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
|
||||
*/
|
||||
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "GEF_SBC610";
|
||||
compatible = "gef,sbc610";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
lbc: localbus@fef05000 {
|
||||
reg = <0xfef05000 0x1000>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe8000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe0000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00008000 // FPGA
|
||||
5 0 0xfc008000 0x00008000 // AFIX FPGA
|
||||
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
|
||||
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,sbc610-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/* Second watchdog available, driver currently supports one.
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,fpga-pic";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8 0x9 0 0>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@7,14000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,sbc610-gpio";
|
||||
reg = <0x7 0x14000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@fef00000 {
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
|
||||
i2c@3000 {
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@25000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
reg = <0xfef08000 0x1000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25fl256s1";
|
||||
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -77,7 +77,7 @@
|
|||
flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,m25p32";
|
||||
compatible = "micron,m25p32", "jedec,spi-nor";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <15000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
partition@u-boot {
|
||||
|
|
@ -166,17 +166,17 @@
|
|||
};
|
||||
};
|
||||
flash@1 {
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
flash@2 {
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
flash@3 {
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <3>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,65 +9,23 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MPC8641HPCN";
|
||||
compatible = "fsl,mpc8641hpcn";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>; // L1
|
||||
i-cache-size = <32768>; // L1
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; // 1G at 0x0
|
||||
};
|
||||
|
||||
localbus@ffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
lbc: localbus@ffe05000 {
|
||||
reg = <0xffe05000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xef800000 0x00800000
|
||||
2 0 0xffdf8000 0x00008000
|
||||
|
|
@ -101,255 +59,77 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc8641@ffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
soc: soc8641@ffe00000 {
|
||||
ranges = <0x00000000 0xffe00000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@25520 {
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@27520 {
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
rmu: rmu@d3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -361,50 +141,35 @@
|
|||
compatible = "fsl,srio-msg-unit";
|
||||
reg = <0x0 0x100>;
|
||||
interrupts = <
|
||||
53 2 /* msg1_tx_irq */
|
||||
54 2>;/* msg1_rx_irq */
|
||||
53 2 0 0 /* msg1_tx_irq */
|
||||
54 2 0 0>;/* msg1_rx_irq */
|
||||
};
|
||||
message-unit@100 {
|
||||
compatible = "fsl,srio-msg-unit";
|
||||
reg = <0x100 0x100>;
|
||||
interrupts = <
|
||||
55 2 /* msg2_tx_irq */
|
||||
56 2>;/* msg2_rx_irq */
|
||||
55 2 0 0 /* msg2_tx_irq */
|
||||
56 2 0 0>;/* msg2_rx_irq */
|
||||
};
|
||||
doorbell-unit@400 {
|
||||
compatible = "fsl,srio-dbell-unit";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <
|
||||
49 2 /* bell_outb_irq */
|
||||
50 2>;/* bell_inb_irq */
|
||||
49 2 0 0 /* bell_outb_irq */
|
||||
50 2 0 0>;/* bell_inb_irq */
|
||||
};
|
||||
port-write-unit@4e0 {
|
||||
compatible = "fsl,srio-port-write-unit";
|
||||
reg = <0x4e0 0x20>;
|
||||
interrupts = <48 2>;
|
||||
interrupts = <48 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe08000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe08000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
||||
|
|
@ -522,10 +287,6 @@
|
|||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
|
@ -545,7 +306,6 @@
|
|||
0x0 0x00010000>;
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#interrupt-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <0xf000 0 0 0 0>;
|
||||
|
|
@ -562,8 +322,7 @@
|
|||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <9 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <9 2 0 0>;
|
||||
};
|
||||
|
||||
i8042@60 {
|
||||
|
|
@ -571,8 +330,7 @@
|
|||
#address-cells = <1>;
|
||||
reg = <1 0x60 1 1 0x64 1>;
|
||||
interrupts = <1 3 12 3>;
|
||||
interrupt-parent =
|
||||
<&i8259>;
|
||||
interrupt-parent = <&i8259>;
|
||||
|
||||
keyboard@0 {
|
||||
reg = <0>;
|
||||
|
|
@ -603,16 +361,14 @@
|
|||
pci1: pcie@ffe09000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xffe09000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
|
|
@ -644,8 +400,7 @@
|
|||
rapidio@ffec0000 {
|
||||
reg = <0xffec0000 0x11000>;
|
||||
compatible = "fsl,srio";
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <48 2>;
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
|
|
@ -661,3 +416,5 @@
|
|||
*/
|
||||
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MPC8641HPCN";
|
||||
|
|
@ -18,56 +18,16 @@
|
|||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
|
||||
};
|
||||
|
||||
localbus@fffe05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
lbc: localbus@fffe05000 {
|
||||
reg = <0x0f 0xffe05000 0x0 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xf 0xef800000 0x00800000
|
||||
2 0 0xf 0xffdf8000 0x00008000
|
||||
|
|
@ -101,276 +61,82 @@
|
|||
};
|
||||
};
|
||||
|
||||
soc8641@fffe00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
soc: soc8641@fffe00000 {
|
||||
ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <10 1>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@25520 {
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
mdio@27520 {
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fffe08000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x0f 0xffe08000 0x0 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
||||
|
|
@ -488,10 +254,6 @@
|
|||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x20000000
|
||||
|
|
@ -511,7 +273,6 @@
|
|||
0x0 0x00010000>;
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#interrupt-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <0xf000 0 0 0 0>;
|
||||
|
|
@ -528,8 +289,7 @@
|
|||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <9 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <9 2 0 0>;
|
||||
};
|
||||
|
||||
i8042@60 {
|
||||
|
|
@ -537,8 +297,7 @@
|
|||
#address-cells = <1>;
|
||||
reg = <1 0x60 1 1 0x64 1>;
|
||||
interrupts = <1 3 12 3>;
|
||||
interrupt-parent =
|
||||
<&i8259>;
|
||||
interrupt-parent = <&i8259>;
|
||||
|
||||
keyboard@0 {
|
||||
reg = <0>;
|
||||
|
|
@ -567,19 +326,16 @@
|
|||
};
|
||||
|
||||
pci1: pcie@fffe09000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x0f 0xffe09000 0x0 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
|
|
@ -603,3 +359,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* MPC8641 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8641-soc", "simple-bus";
|
||||
bus-frequency = <0>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
serial@4600 {
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
dma@21300 {
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
};
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
ethernet@24000 {
|
||||
model = "TSEC";
|
||||
};
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
ethernet@25000 {
|
||||
model = "TSEC";
|
||||
};
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
ethernet@26000 {
|
||||
model = "TSEC";
|
||||
};
|
||||
/include/ "pq3-etsec1-3.dtsi"
|
||||
ethernet@27000 {
|
||||
model = "TSEC";
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
};
|
||||
msi@41800 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
};
|
||||
msi@41a00 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <24 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* MPC8641 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -70,12 +70,12 @@
|
|||
fsl,espi-num-chipselects = <2>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "atmel,at25df641";
|
||||
compatible = "atmel,at25df641", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
flash@1 {
|
||||
compatible = "atmel,at25df641";
|
||||
compatible = "atmel,at25df641", "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* input clock */
|
||||
spi-max-frequency = <40000000>;
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
partition@0 {
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80";
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* P2041RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,19 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
phy_rgmii_0 = &phy_rgmii_0;
|
||||
phy_rgmii_1 = &phy_rgmii_1;
|
||||
phy_sgmii_2 = &phy_sgmii_2;
|
||||
phy_sgmii_3 = &phy_sgmii_3;
|
||||
phy_sgmii_4 = &phy_sgmii_4;
|
||||
phy_sgmii_1c = &phy_sgmii_1c;
|
||||
phy_sgmii_1d = &phy_sgmii_1d;
|
||||
phy_sgmii_1e = &phy_sgmii_1e;
|
||||
phy_sgmii_1f = &phy_sgmii_1f;
|
||||
phy_xgmii_2 = &phy_xgmii_2;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
|
@ -83,7 +96,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
|
|
@ -137,6 +150,83 @@
|
|||
usb1: usb@211000 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
mdio@e1120 {
|
||||
phy_rgmii_0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy_rgmii_1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy_sgmii_2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
phy_sgmii_3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
phy_sgmii_4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
phy_sgmii_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_3>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_4>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy_rgmii_1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_0>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xgmii_2>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
mdio@f1000 {
|
||||
phy_xgmii_2: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* P3041DS Device Tree Source
|
||||
*
|
||||
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,20 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases{
|
||||
phy_rgmii_0 = &phy_rgmii_0;
|
||||
phy_rgmii_1 = &phy_rgmii_1;
|
||||
phy_sgmii_1c = &phy_sgmii_1c;
|
||||
phy_sgmii_1d = &phy_sgmii_1d;
|
||||
phy_sgmii_1e = &phy_sgmii_1e;
|
||||
phy_sgmii_1f = &phy_sgmii_1f;
|
||||
phy_xgmii_1 = &phy_xgmii_1;
|
||||
phy_xgmii_2 = &phy_xgmii_2;
|
||||
emi1_rgmii = &hydra_mdio_rgmii;
|
||||
emi1_sgmii = &hydra_mdio_sgmii;
|
||||
emi2_xgmii = &hydra_mdio_xgmii;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
|
@ -83,7 +97,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <35000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
|
|
@ -150,6 +164,52 @@
|
|||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000{
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_1c>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_1d>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_1e>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy_sgmii_1f>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xgmii_1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
hydra_mdio_xgmii: mdio@f1000 {
|
||||
status = "disabled";
|
||||
|
||||
phy_xgmii_1: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
phy_xgmii_2: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
|
|
@ -215,8 +275,58 @@
|
|||
};
|
||||
|
||||
board-control@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0 0x30>;
|
||||
ranges = <0 3 0 0x30>;
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
reg = <9 1>;
|
||||
mux-mask = <0x78>;
|
||||
|
||||
hydra_mdio_rgmii: rgmii-mdio@8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <8>;
|
||||
status = "disabled";
|
||||
|
||||
phy_rgmii_0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy_rgmii_1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_mdio_sgmii: sgmii-mdio@28 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x28>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* P4080DS Device Tree Source
|
||||
*
|
||||
* Copyright 2009 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2009 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,20 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
phy_rgmii = &phyrgmii;
|
||||
phy5_slot3 = &phy5slot3;
|
||||
phy6_slot3 = &phy6slot3;
|
||||
phy7_slot3 = &phy7slot3;
|
||||
phy8_slot3 = &phy8slot3;
|
||||
emi1_slot3 = &p4080mdio2;
|
||||
emi1_slot4 = &p4080mdio1;
|
||||
emi1_slot5 = &p4080mdio3;
|
||||
emi1_rgmii = &p4080mdio0;
|
||||
emi2_slot4 = &p4080xmdio1;
|
||||
emi2_slot5 = &p4080xmdio3;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
|
@ -84,7 +98,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
|
|
@ -137,6 +151,60 @@
|
|||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy10>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
|
||||
fman@500000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy5>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy6>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy7>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy8>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy11>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
|
|
@ -213,6 +281,120 @@
|
|||
};
|
||||
};
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-gpio", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
gpios = <&gpio0 1 0>, <&gpio0 0 0>;
|
||||
|
||||
p4080mdio0: mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
phyrgmii: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
p4080mdio1: mdio@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
phy5: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy6: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy7: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy8: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
p4080mdio2: mdio@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
|
||||
phy5slot3: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy6slot3: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy7slot3: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy8slot3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
p4080mdio3: mdio@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
phy0: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio-mux-emi2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-gpio", "mdio-mux";
|
||||
mdio-parent-bus = <&xmdio0>;
|
||||
gpios = <&gpio0 3 0>, <&gpio0 2 0>;
|
||||
|
||||
p4080xmdio1: mdio@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
phy11: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
p4080xmdio3: mdio@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
phy10: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "p4080si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* P5020DS Device Tree Source
|
||||
*
|
||||
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,20 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
phy_rgmii_0 = &phy_rgmii_0;
|
||||
phy_rgmii_1 = &phy_rgmii_1;
|
||||
phy_sgmii_1c = &phy_sgmii_1c;
|
||||
phy_sgmii_1d = &phy_sgmii_1d;
|
||||
phy_sgmii_1e = &phy_sgmii_1e;
|
||||
phy_sgmii_1f = &phy_sgmii_1f;
|
||||
phy_xgmii_1 = &phy_xgmii_1;
|
||||
phy_xgmii_2 = &phy_xgmii_2;
|
||||
emi1_rgmii = &hydra_mdio_rgmii;
|
||||
emi1_sgmii = &hydra_mdio_sgmii;
|
||||
emi2_xgmii = &hydra_mdio_xgmii;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
|
@ -83,7 +97,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
|
|
@ -150,6 +164,52 @@
|
|||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_1c>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_1d>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_1e>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy_sgmii_1f>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xgmii_1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
hydra_mdio_xgmii: mdio@f1000 {
|
||||
status = "disabled";
|
||||
|
||||
phy_xgmii_1: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
phy_xgmii_2: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
|
|
@ -215,8 +275,58 @@
|
|||
};
|
||||
|
||||
board-control@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0 0x30>;
|
||||
ranges = <0 3 0 0x30>;
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
reg = <9 1>;
|
||||
mux-mask = <0x78>;
|
||||
|
||||
hydra_mdio_rgmii: rgmii-mdio@8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <8>;
|
||||
status = "disabled";
|
||||
|
||||
phy_rgmii_0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy_rgmii_1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_mdio_sgmii: sgmii-mdio@28 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x28>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* P5040DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,32 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases{
|
||||
phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
|
||||
phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
|
||||
phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
|
||||
phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
|
||||
phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
|
||||
phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
|
||||
phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
|
||||
phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
|
||||
phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
|
||||
phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
|
||||
phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
|
||||
phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
|
||||
phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
|
||||
phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
|
||||
phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
|
||||
phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
|
||||
hydra_rg = &hydra_rg;
|
||||
hydra_sg_slot2 = &hydra_sg_slot2;
|
||||
hydra_sg_slot3 = &hydra_sg_slot3;
|
||||
hydra_sg_slot5 = &hydra_sg_slot5;
|
||||
hydra_sg_slot6 = &hydra_sg_slot6;
|
||||
hydra_xg_slot1 = &hydra_xg_slot1;
|
||||
hydra_xg_slot2 = &hydra_xg_slot2;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
|
@ -83,7 +109,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
compatible = "spansion,s25sl12801", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
partition@u-boot {
|
||||
|
|
@ -147,6 +173,62 @@
|
|||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_0>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xgmii_slot_2>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
|
||||
fman@500000 {
|
||||
ethernet@e0000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xgmii_slot_1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lbc: localbus@ffe124000 {
|
||||
|
|
@ -200,8 +282,158 @@
|
|||
};
|
||||
|
||||
board-control@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
|
||||
reg = <3 0 0x40>;
|
||||
ranges = <0 3 0 0x40>;
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
reg = <9 1>;
|
||||
mux-mask = <0x78>;
|
||||
|
||||
hydra_rg:rgmii-mdio@8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <8>;
|
||||
status = "disabled";
|
||||
|
||||
phy_rgmii_0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy_rgmii_1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_sg_slot2: sgmii-mdio@28 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x28>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_slot2_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot2_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot2_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot2_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_sg_slot3: sgmii-mdio@68 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x68>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_slot3_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot3_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot3_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot3_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_sg_slot5: sgmii-mdio@38 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x38>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_slot5_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot5_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot5_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot5_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
hydra_sg_slot6: sgmii-mdio@48 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x48>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_slot6_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot6_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot6_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_slot6_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio-mux-emi2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&xmdio0>;
|
||||
reg = <9 1>;
|
||||
mux-mask = <0x06>;
|
||||
|
||||
hydra_xg_slot1: hydra-xg-slot1@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
|
||||
phy_xgmii_slot_1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
hydra_xg_slot2: hydra-xg-slot2@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
phy_xgmii_slot_2: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -420,6 +420,7 @@
|
|||
fsl,iommu-parent = <&pamu4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-raid1.0-0.dtsi"
|
||||
/include/ "qoriq-qman1.dtsi"
|
||||
/include/ "qoriq-bman1.dtsi"
|
||||
|
||||
|
|
|
|||
|
|
@ -73,6 +73,12 @@
|
|||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
raideng = &raideng;
|
||||
raideng_jr0 = &raideng_jr0;
|
||||
raideng_jr1 = &raideng_jr1;
|
||||
raideng_jr2 = &raideng_jr2;
|
||||
raideng_jr3 = &raideng_jr3;
|
||||
|
||||
fman0 = &fman0;
|
||||
fman1 = &fman1;
|
||||
ethernet0 = &enet0;
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ fman@400000 {
|
|||
reg = <0xe0000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy0>;
|
||||
};
|
||||
|
||||
mdio@e1000 {
|
||||
|
|
@ -62,5 +63,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe1000 0x1000>;
|
||||
|
||||
pcsphy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ fman@400000 {
|
|||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf0000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
|
||||
pcsphy-handle = <&pcsphy6>;
|
||||
};
|
||||
|
||||
mdio@f1000 {
|
||||
|
|
@ -59,5 +60,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ fman@400000 {
|
|||
reg = <0xe2000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy1>;
|
||||
};
|
||||
|
||||
mdio@e3000 {
|
||||
|
|
@ -62,5 +63,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe3000 0x1000>;
|
||||
|
||||
pcsphy1: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ fman@400000 {
|
|||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf2000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
|
||||
pcsphy-handle = <&pcsphy7>;
|
||||
};
|
||||
|
||||
mdio@f3000 {
|
||||
|
|
@ -59,5 +60,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf3000 0x1000>;
|
||||
|
||||
pcsphy7: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xe0000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy0>;
|
||||
};
|
||||
|
||||
mdio@e1000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe1000 0x1000>;
|
||||
|
||||
pcsphy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xe2000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy1>;
|
||||
};
|
||||
|
||||
mdio@e3000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe3000 0x1000>;
|
||||
|
||||
pcsphy1: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xe4000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy2>;
|
||||
};
|
||||
|
||||
mdio@e5000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe5000 0x1000>;
|
||||
|
||||
pcsphy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xe6000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy3>;
|
||||
};
|
||||
|
||||
mdio@e7000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe7000 0x1000>;
|
||||
|
||||
pcsphy3: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xe8000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy4>;
|
||||
};
|
||||
|
||||
mdio@e9000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe9000 0x1000>;
|
||||
|
||||
pcsphy4: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@400000 {
|
|||
reg = <0xea000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy5>;
|
||||
};
|
||||
|
||||
mdio@eb000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@400000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xeb000 0x1000>;
|
||||
|
||||
pcsphy5: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ fman@500000 {
|
|||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf0000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
|
||||
pcsphy-handle = <&pcsphy14>;
|
||||
};
|
||||
|
||||
mdio@f1000 {
|
||||
|
|
@ -59,5 +60,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
|
||||
pcsphy14: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ fman@500000 {
|
|||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf2000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
|
||||
pcsphy-handle = <&pcsphy15>;
|
||||
};
|
||||
|
||||
mdio@f3000 {
|
||||
|
|
@ -59,5 +60,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf3000 0x1000>;
|
||||
|
||||
pcsphy15: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xe0000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy8>;
|
||||
};
|
||||
|
||||
mdio@e1000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe1000 0x1000>;
|
||||
|
||||
pcsphy8: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xe2000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy9>;
|
||||
};
|
||||
|
||||
mdio@e3000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe3000 0x1000>;
|
||||
|
||||
pcsphy9: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xe4000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy10>;
|
||||
};
|
||||
|
||||
mdio@e5000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe5000 0x1000>;
|
||||
|
||||
pcsphy10: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xe6000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy11>;
|
||||
};
|
||||
|
||||
mdio@e7000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe7000 0x1000>;
|
||||
|
||||
pcsphy11: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xe8000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy12>;
|
||||
};
|
||||
|
||||
mdio@e9000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe9000 0x1000>;
|
||||
|
||||
pcsphy12: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ fman@500000 {
|
|||
reg = <0xea000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
|
||||
ptp-timer = <&ptp_timer1>;
|
||||
pcsphy-handle = <&pcsphy13>;
|
||||
};
|
||||
|
||||
mdio@eb000 {
|
||||
|
|
@ -58,5 +59,9 @@ fman@500000 {
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xeb000 0x1000>;
|
||||
|
||||
pcsphy13: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* SBC8641D Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Wind River Systems Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc8641si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SBC8641D";
|
||||
compatible = "wind,sbc8641";
|
||||
|
||||
aliases {
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; // 512M at 0x0
|
||||
};
|
||||
|
||||
lbc: localbus@f8005000 {
|
||||
reg = <0xf8005000 0x1000>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xf0000000 0x00010000 // 64KB EEPROM
|
||||
2 0 0xf1000000 0x00100000 // EPLD (1MB)
|
||||
3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
|
||||
4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
|
||||
6 0 0xf4000000 0x00100000 // LCD display (1MB)
|
||||
7 0 0xe8000000 0x04000000>; // 64MB OneNAND
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x01000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "dtb";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "fs";
|
||||
reg = <0x00500000 0x00a00000>;
|
||||
};
|
||||
partition@700000 {
|
||||
label = "firmware";
|
||||
reg = <0x00f00000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
epld@2,0 {
|
||||
compatible = "wrs,epld-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <2 0 0x100000>;
|
||||
ranges = <0 0 5 0 1 // User switches
|
||||
1 0 5 1 1 // Board ID/Rev
|
||||
3 0 5 3 1>; // LEDs
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@f8000000 {
|
||||
ranges = <0x00000000 0xf8000000 0x00100000>;
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
phy0: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy2: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy3: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@f8008000 {
|
||||
reg = <0xf8008000 0x1000>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci1: pcie@f8009000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf8009000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0000 0 0 1 &mpic 4 1
|
||||
0x0000 0 0 2 &mpic 5 1
|
||||
0x0000 0 0 3 &mpic 6 1
|
||||
0x0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -79,7 +79,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25fl512s";
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clk */
|
||||
};
|
||||
|
|
@ -111,6 +111,47 @@
|
|||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
fm1mac1: ethernet@e0000 {
|
||||
phy-handle = <&sgmii_rtk_phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
sleep = <&rcpm 0x80000000>;
|
||||
};
|
||||
|
||||
fm1mac2: ethernet@e2000 {
|
||||
sleep = <&rcpm 0x40000000>;
|
||||
};
|
||||
|
||||
fm1mac3: ethernet@e4000 {
|
||||
phy-handle = <&sgmii_aqr_phy3>;
|
||||
phy-connection-type = "sgmii-2500";
|
||||
sleep = <&rcpm 0x20000000>;
|
||||
};
|
||||
|
||||
fm1mac4: ethernet@e6000 {
|
||||
phy-handle = <&rgmii_rtk_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
sleep = <&rcpm 0x10000000>;
|
||||
};
|
||||
|
||||
|
||||
mdio0: mdio@fc000 {
|
||||
rgmii_rtk_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
sgmii_rtk_phy2: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
xmdio0: mdio@fd000 {
|
||||
sgmii_aqr_phy3: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11"; /* 16MB */
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
|
@ -95,7 +95,7 @@
|
|||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040"; /* 512KB */
|
||||
compatible = "sst,sst25wf040", "jedec,spi-nor"; /* 512KB */
|
||||
reg = <1>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
|
@ -103,7 +103,7 @@
|
|||
flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "eon,en25s64"; /* 8MB */
|
||||
compatible = "eon,en25s64", "jedec,spi-nor"; /* 8MB */
|
||||
reg = <2>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512ax3";
|
||||
compatible = "micron,n25q512ax3", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clk */
|
||||
};
|
||||
|
|
@ -140,6 +140,51 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
fm1mac1: ethernet@e0000 {
|
||||
phy-handle = <&xg_aqr105_phy3>;
|
||||
phy-connection-type = "xgmii";
|
||||
sleep = <&rcpm 0x80000000>;
|
||||
};
|
||||
|
||||
fm1mac2: ethernet@e2000 {
|
||||
sleep = <&rcpm 0x40000000>;
|
||||
};
|
||||
|
||||
fm1mac3: ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
sleep = <&rcpm 0x20000000>;
|
||||
};
|
||||
|
||||
fm1mac4: ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
sleep = <&rcpm 0x10000000>;
|
||||
};
|
||||
|
||||
|
||||
mdio0: mdio@fc000 {
|
||||
rgmii_phy1: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
rgmii_phy2: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
xmdio0: mdio@fd000 {
|
||||
xg_aqr105_phy3: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x1>;
|
||||
};
|
||||
sg_2500_aqr105_phy4: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T1040RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -38,6 +38,36 @@
|
|||
/ {
|
||||
model = "fsl,T1040RDB";
|
||||
compatible = "fsl,T1040RDB";
|
||||
|
||||
aliases {
|
||||
phy_sgmii_2 = &phy_sgmii_2;
|
||||
};
|
||||
|
||||
soc@ffe000000 {
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
phy_sgmii_2: ethernet-phy@03 {
|
||||
reg = <0x03>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,t1040rdb-cpld";
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T1042RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -38,6 +38,34 @@
|
|||
/ {
|
||||
model = "fsl,T1042RDB";
|
||||
compatible = "fsl,T1042RDB";
|
||||
|
||||
aliases {
|
||||
phy_sgmii_2 = &phy_sgmii_2;
|
||||
};
|
||||
|
||||
soc@ffe000000 {
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_sgmii_2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
phy_sgmii_2: ethernet-phy@03 {
|
||||
reg = <0x03>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,t1042rdb-cpld";
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T1042RDB_PI Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -38,11 +38,13 @@
|
|||
/ {
|
||||
model = "fsl,T1042RDB_PI";
|
||||
compatible = "fsl,T1042RDB_PI";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
cpld@3,0 {
|
||||
compatible = "fsl,t1042rdb_pi-cpld";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
i2c@118000 {
|
||||
rtc@68 {
|
||||
|
|
@ -51,6 +53,20 @@
|
|||
interrupts = <0x2 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512ax3";
|
||||
compatible = "micron,n25q512ax3", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* input clock */
|
||||
spi-max-frequency = <10000000>;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T104xQDS Device Tree Source
|
||||
*
|
||||
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -38,6 +38,33 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
emi1_rgmii0 = &t1040mdio0;
|
||||
emi1_rgmii1 = &t1040mdio1;
|
||||
emi1_slot3 = &t1040mdio3;
|
||||
emi1_slot5 = &t1040mdio5;
|
||||
emi1_slot6 = &t1040mdio6;
|
||||
emi1_slot7 = &t1040mdio7;
|
||||
rgmii_phy1 = &rgmii_phy1;
|
||||
rgmii_phy2 = &rgmii_phy2;
|
||||
phy_s3_01 = &phy_s3_01;
|
||||
phy_s3_02 = &phy_s3_02;
|
||||
phy_s3_03 = &phy_s3_03;
|
||||
phy_s3_04 = &phy_s3_04;
|
||||
phy_s5_01 = &phy_s5_01;
|
||||
phy_s5_02 = &phy_s5_02;
|
||||
phy_s5_03 = &phy_s5_03;
|
||||
phy_s5_04 = &phy_s5_04;
|
||||
phy_s6_01 = &phy_s6_01;
|
||||
phy_s6_02 = &phy_s6_02;
|
||||
phy_s6_03 = &phy_s6_03;
|
||||
phy_s6_04 = &phy_s6_04;
|
||||
phy_s7_01 = &phy_s7_01;
|
||||
phy_s7_02 = &phy_s7_02;
|
||||
phy_s7_03 = &phy_s7_03;
|
||||
phy_s7_04 = &phy_s7_04;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -85,6 +112,128 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
ranges = <0 3 0 0x300>;
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
reg = <0x54 1>;
|
||||
mux-mask = <0xe0>;
|
||||
|
||||
t1040mdio0: mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x00>;
|
||||
status = "disabled";
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
t1040mdio1: mdio@20 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x20>;
|
||||
status = "disabled";
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
t1040mdio3: mdio@60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x60>;
|
||||
status = "disabled";
|
||||
|
||||
phy_s3_01: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_s3_02: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_s3_03: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_s3_04: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t1040mdio5: mdio@a0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa0>;
|
||||
|
||||
phy_s5_01: ethernet-phy@1c {
|
||||
reg = <0x14>;
|
||||
};
|
||||
|
||||
phy_s5_02: ethernet-phy@1d {
|
||||
reg = <0x15>;
|
||||
};
|
||||
|
||||
phy_s5_03: ethernet-phy@1e {
|
||||
reg = <0x16>;
|
||||
};
|
||||
|
||||
phy_s5_04: ethernet-phy@1f {
|
||||
reg = <0x17>;
|
||||
};
|
||||
};
|
||||
|
||||
t1040mdio6: mdio@c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc0>;
|
||||
|
||||
phy_s6_01: ethernet-phy@1c {
|
||||
reg = <0x18>;
|
||||
};
|
||||
|
||||
phy_s6_02: ethernet-phy@1d {
|
||||
reg = <0x19>;
|
||||
};
|
||||
|
||||
phy_s6_03: ethernet-phy@1e {
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
phy_s6_04: ethernet-phy@1f {
|
||||
reg = <0x1b>;
|
||||
};
|
||||
};
|
||||
|
||||
t1040mdio7: mdio@e0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xe0>;
|
||||
status = "disabled";
|
||||
|
||||
phy_s7_01: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_s7_02: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_s7_03: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_s7_04: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -112,7 +261,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11";
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -129,6 +278,33 @@
|
|||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy_s7_03>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T1040RDB/T1042RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -33,6 +33,12 @@
|
|||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
phy_rgmii_0 = &phy_rgmii_0;
|
||||
phy_rgmii_1 = &phy_rgmii_1;
|
||||
phy_sgmii_2 = &phy_sgmii_2;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -103,10 +109,15 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512a";
|
||||
compatible = "micron,n25q512a", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clock */
|
||||
};
|
||||
slic@3 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <3>;
|
||||
spi-max-frequency = <2000000>; /* input clock */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
|
|
@ -125,6 +136,31 @@
|
|||
};
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy_rgmii_0>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_rgmii_1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
mdio0: mdio@fc000 {
|
||||
phy_sgmii_2: ethernet-phy@03 {
|
||||
reg = <0x03>;
|
||||
};
|
||||
|
||||
phy_rgmii_0: ethernet-phy@01 {
|
||||
reg = <0x01>;
|
||||
};
|
||||
|
||||
phy_rgmii_1: ethernet-phy@02 {
|
||||
reg = <0x02>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T2080QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -42,6 +42,12 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
emi1_slot1 = &t2080mdio2;
|
||||
emi1_slot2 = &t2080mdio3;
|
||||
emi1_slot3 = &t2080mdio4;
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
|
|
@ -54,4 +60,154 @@
|
|||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_s3_1e>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_s3_1f>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_sgmii_s2_1e>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&phy_sgmii_s2_1d>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_xaui_slot3>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&phy_sgmii_s3_1f>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
phy_xaui_slot3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&boardctrl {
|
||||
mdio-mux-emi1 {
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x54 1>;
|
||||
mux-mask = <0xe0>;
|
||||
|
||||
t2080mdio0: mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
t2080mdio1: mdio@20 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x20>;
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
t2080mdio2: mdio@40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_s1_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2080mdio3: mdio@c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc0>;
|
||||
|
||||
phy_sgmii_s2_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2080mdio4: mdio@60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x60>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_s3_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "t2080si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T2080PCIe-RDB Board Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -54,4 +54,69 @@
|
|||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&xg_aq1202_phy3>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&xg_aq1202_phy4>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&xg_cs4315_phy1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&xg_cs4315_phy2>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
xg_cs4315_phy1: ethernet-phy@c {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0xc>;
|
||||
};
|
||||
|
||||
xg_cs4315_phy2: ethernet-phy@d {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0xd>;
|
||||
};
|
||||
|
||||
xg_aq1202_phy3: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
xg_aq1202_phy4: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "t2080si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T2081QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,225 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
emi1_slot1 = &t2081mdio2;
|
||||
emi1_slot2 = &t2081mdio3;
|
||||
emi1_slot3 = &t2081mdio4;
|
||||
emi1_slot5 = &t2081mdio5;
|
||||
emi1_slot6 = &t2081mdio6;
|
||||
emi1_slot7 = &t2081mdio7;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy_sgmii_s7_1c>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy_sgmii_s7_1d>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phy_sgmii_s3_1c>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&phy_sgmii_s7_1f>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&phy_sgmii_s2_1c>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&phy_sgmii_s7_1e>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&boardctrl {
|
||||
mdio-mux-emi1 {
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x54 1>;
|
||||
mux-mask = <0xe0>;
|
||||
|
||||
t2081mdio0: mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio1: mdio@20 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x20>;
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio2: mdio@40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40>;
|
||||
|
||||
phy_sgmii_s1_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s1_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio3: mdio@60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x60>;
|
||||
|
||||
phy_sgmii_s2_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s2_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio4: mdio@80 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_s3_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s3_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio5: mdio@a0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xa0>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_s5_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s5_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s5_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s5_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio6: mdio@c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc0>;
|
||||
status = "disabled";
|
||||
|
||||
phy_sgmii_s6_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s6_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s6_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s6_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t2081mdio7: mdio@e0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xe0>;
|
||||
|
||||
phy_sgmii_s7_1c: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
phy_sgmii_s7_1d: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
phy_sgmii_s7_1e: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
phy_sgmii_s7_1f: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "t2081si-post.dtsi"
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q128a11"; /* 16MB */
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -120,7 +120,7 @@
|
|||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
compatible = "sst,sst25wf040", "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <35000000>;
|
||||
};
|
||||
|
|
@ -128,7 +128,7 @@
|
|||
flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "eon,en25s64";
|
||||
compatible = "eon,en25s64", "jedec,spi-nor";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <35000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q512a";
|
||||
compatible = "micron,n25q512a", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>; /* input clock */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T4240QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,44 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases{
|
||||
phy_rgmii1 = &phyrgmii1;
|
||||
phy_rgmii2 = &phyrgmii2;
|
||||
phy_sgmii3 = &phy3;
|
||||
phy_sgmii4 = &phy4;
|
||||
phy_sgmii11 = &phy11;
|
||||
phy_sgmii12 = &phy12;
|
||||
sgmii_phy11 = &sgmiiphy11;
|
||||
sgmii_phy12 = &sgmiiphy12;
|
||||
sgmii_phy13 = &sgmiiphy13;
|
||||
sgmii_phy14 = &sgmiiphy14;
|
||||
sgmii_phy21 = &sgmiiphy21;
|
||||
sgmii_phy22 = &sgmiiphy22;
|
||||
sgmii_phy23 = &sgmiiphy23;
|
||||
sgmii_phy24 = &sgmiiphy24;
|
||||
sgmii_phy31 = &sgmiiphy31;
|
||||
sgmii_phy32 = &sgmiiphy32;
|
||||
sgmii_phy33 = &sgmiiphy33;
|
||||
sgmii_phy34 = &sgmiiphy34;
|
||||
sgmii_phy41 = &sgmiiphy41;
|
||||
sgmii_phy42 = &sgmiiphy42;
|
||||
sgmii_phy43 = &sgmiiphy43;
|
||||
sgmii_phy44 = &sgmiiphy44;
|
||||
phy_xfi1 = &xfiphy1;
|
||||
phy_xfi2 = &xfiphy2;
|
||||
phy_xfi3 = &xfiphy3;
|
||||
phy_xfi4 = &xfiphy4;
|
||||
xfi_pcs_mdio1 = &xfimdio0;
|
||||
xfi_pcs_mdio2 = &xfimdio1;
|
||||
xfi_pcs_mdio3 = &xfimdio2;
|
||||
xfi_pcs_mdio4 = &xfimdio3;
|
||||
emi1_rgmii = &t4240mdio0;
|
||||
emi1_slot1 = &t4240mdio1;
|
||||
emi1_slot2 = &t4240mdio2;
|
||||
emi1_slot3 = &t4240mdio3;
|
||||
emi1_slot4 = &t4240mdio4;
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
|
|
@ -91,8 +129,190 @@
|
|||
};
|
||||
|
||||
board-control@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
ranges = <0 3 0 0x300>;
|
||||
|
||||
mdio-mux-emi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio1>;
|
||||
reg = <0x54 1>;
|
||||
mux-mask = <0xe0>;
|
||||
|
||||
t4240mdio0: mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
phyrgmii1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phyrgmii2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
t4240mdio1: mdio@20 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x20>;
|
||||
status = "disabled";
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
phy4: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
sgmiiphy11: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
sgmiiphy12: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmiiphy13: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmiiphy14: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t4240mdio2: mdio@40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40>;
|
||||
status = "disabled";
|
||||
|
||||
phy5: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
phy6: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
phy7: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
phy8: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
sgmiiphy21: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
sgmiiphy22: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmiiphy23: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmiiphy24: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t4240mdio3: mdio@60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x60>;
|
||||
status = "disabled";
|
||||
|
||||
phy9: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
phy10: ethernet-phy@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
phy11: ethernet-phy@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
phy12: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
};
|
||||
|
||||
sgmiiphy31: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
sgmiiphy32: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmiiphy33: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmiiphy34: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
t4240mdio4: mdio@80 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80>;
|
||||
status = "disabled";
|
||||
|
||||
phy13: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
};
|
||||
|
||||
phy14: ethernet-phy@d {
|
||||
reg = <0xd>;
|
||||
};
|
||||
|
||||
phy15: ethernet-phy@e {
|
||||
reg = <0xe>;
|
||||
};
|
||||
|
||||
phy16: ethernet-phy@f {
|
||||
reg = <0xf>;
|
||||
};
|
||||
|
||||
sgmiiphy41: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
sgmiiphy42: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmiiphy43: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmiiphy44: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -138,7 +358,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
compatible = "sst,sst25wf040", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -234,6 +454,184 @@
|
|||
sdhc@114000 {
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
port@83000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@84000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@85000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@86000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@87000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy5>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy6>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy7>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy8>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phyrgmii2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&xauiphy1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&xauiphy2>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
xfimdio0: mdio@f1000 {
|
||||
status = "disabled";
|
||||
|
||||
xfiphy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
xfimdio1: mdio@f3000 {
|
||||
status = "disabled";
|
||||
|
||||
xfiphy2: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fman@500000 {
|
||||
port@84000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@85000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@86000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@87000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&phy13>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&phy14>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&phy15>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&phy16>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&phyrgmii1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&phy10>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&xauiphy3>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&xauiphy4>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
xfimdio2: mdio@f1000 {
|
||||
status = "disabled";
|
||||
|
||||
xfiphy3: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
xfimdio3: mdio@f3000 {
|
||||
status = "disabled";
|
||||
|
||||
xfiphy4: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
xauiphy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
xauiphy2: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
xauiphy3: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
xauiphy4: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* T4240RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -41,6 +41,17 @@
|
|||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
sgmii_phy21 = &sgmiiphy21;
|
||||
sgmii_phy22 = &sgmiiphy22;
|
||||
sgmii_phy23 = &sgmiiphy23;
|
||||
sgmii_phy24 = &sgmiiphy24;
|
||||
sgmii_phy41 = &sgmiiphy41;
|
||||
sgmii_phy42 = &sgmiiphy42;
|
||||
sgmii_phy43 = &sgmiiphy43;
|
||||
sgmii_phy44 = &sgmiiphy44;
|
||||
};
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
|
|
@ -107,7 +118,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
compatible = "sst,sst25wf040", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
|
|
@ -136,6 +147,142 @@
|
|||
sdhc@114000 {
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
};
|
||||
|
||||
fman@400000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&sgmiiphy21>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&sgmiiphy22>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&sgmiiphy23>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&sgmiiphy24>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&xfiphy1>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&xfiphy2>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
|
||||
fman@500000 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&sgmiiphy41>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&sgmiiphy42>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&sgmiiphy43>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&sgmiiphy44>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&xfiphy3>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&xfiphy4>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
sgmiiphy21: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
sgmiiphy22: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
sgmiiphy23: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
sgmiiphy24: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
sgmiiphy41: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
sgmiiphy42: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
sgmiiphy43: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
sgmiiphy44: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
xfiphy1: ethernet-phy@10 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x10>;
|
||||
};
|
||||
|
||||
xfiphy2: ethernet-phy@11 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
xfiphy3: ethernet-phy@13 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
xfiphy4: ethernet-phy@12 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x12>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
|
|
|
|||
|
|
@ -1,425 +0,0 @@
|
|||
/*
|
||||
* GE PPC9A Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "GEF_PPC9A";
|
||||
compatible = "gef,ppc9a";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
localbus@fef05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
reg = <0xfef05000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe8000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe0000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00008000 // FPGA
|
||||
5 0 0xfc008000 0x00008000 // AFIX FPGA
|
||||
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
|
||||
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,ppc9a-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,ppc9a-fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/* Second watchdog available, driver currently supports one.
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8
|
||||
0x9>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@7,14000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
|
||||
reg = <0x7 0x14000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fef00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8641-soc", "simple-bus";
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
bus-frequency = <33333333>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c1: i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2: i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x2a 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x1c 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfef08000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x18 0x2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,459 +0,0 @@
|
|||
/*
|
||||
* GE SBC310 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "GEF_SBC310";
|
||||
compatible = "gef,sbc310";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
localbus@fef05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
reg = <0xfef05000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe0000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe8000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00010000>; // FPGA
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x01000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x01000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,sbc310-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/*
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
|
||||
"gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8
|
||||
0x9>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@4,8000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,sbc310-gpio";
|
||||
reg = <0x4 0x8000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fef00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8641-soc", "simple-bus";
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
bus-frequency = <33333333>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c1: i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2: i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x2a 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x1c 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfef08000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x18 0x2>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@fef09000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfef09000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x19 0x2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xc0000000
|
||||
0x02000000 0x0 0xc0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,423 +0,0 @@
|
|||
/*
|
||||
* GE SBC610 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Based on: SBS CM6 Device Tree Source
|
||||
* Copyright 2007 SBS Technologies GmbH & Co. KG
|
||||
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "GEF_SBC610";
|
||||
compatible = "gef,sbc610";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; // set by uboot
|
||||
};
|
||||
|
||||
localbus@fef05000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
reg = <0xfef05000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xe8000000 0x08000000 // Paged Flash 0
|
||||
2 0 0xe0000000 0x08000000 // Paged Flash 1
|
||||
3 0 0xfc100000 0x00020000 // NVRAM
|
||||
4 0 0xfc000000 0x00008000 // FPGA
|
||||
5 0 0xfc008000 0x00008000 // AFIX FPGA
|
||||
6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
|
||||
7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
|
||||
|
||||
/* flash@0,0 is a mirror of part of the memory in flash@1,0
|
||||
flash@0,0 {
|
||||
compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
|
||||
reg = <0x0 0x0 0x1000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x0 0x1000000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "gef,sbc610-paged-flash", "cfi-flash";
|
||||
reg = <0x1 0x0 0x8000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "user";
|
||||
reg = <0x0 0x7800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "firmware";
|
||||
reg = <0x7800000 0x800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@3,0 {
|
||||
device_type = "nvram";
|
||||
compatible = "simtek,stk14ca8";
|
||||
reg = <0x3 0x0 0x20000>;
|
||||
};
|
||||
|
||||
fpga@4,0 {
|
||||
compatible = "gef,fpga-regs";
|
||||
reg = <0x4 0x0 0x40>;
|
||||
};
|
||||
|
||||
wdt@4,2000 {
|
||||
compatible = "gef,fpga-wdt";
|
||||
reg = <0x4 0x2000 0x8>;
|
||||
interrupts = <0x1a 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
/* Second watchdog available, driver currently supports one.
|
||||
wdt@4,2010 {
|
||||
compatible = "gef,fpga-wdt";
|
||||
reg = <0x4 0x2010 0x8>;
|
||||
interrupts = <0x1b 0x4>;
|
||||
interrupt-parent = <&gef_pic>;
|
||||
};
|
||||
*/
|
||||
gef_pic: pic@4,4000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "gef,fpga-pic";
|
||||
reg = <0x4 0x4000 0x20>;
|
||||
interrupts = <0x8
|
||||
0x9>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
};
|
||||
gef_gpio: gpio@7,14000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "gef,sbc610-gpio";
|
||||
reg = <0x7 0x14000 0x24>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fef00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xfef00000 0x00100000>;
|
||||
bus-frequency = <33333333>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c1: i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
hwmon@48 {
|
||||
compatible = "national,lm92";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
hwmon@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
rtc@51 {
|
||||
compatible = "epson,rx8581";
|
||||
reg = <0x00000051>;
|
||||
};
|
||||
|
||||
eti@6b {
|
||||
compatible = "dallas,ds1682";
|
||||
reg = <0x6b>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2: i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x9 0x4>;
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&gef_pic>;
|
||||
interrupts = <0x8 0x4>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "gmii";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x2a 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <0x1c 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
msi-available-ranges = <0 0x100>;
|
||||
interrupts = <
|
||||
0xe0 0
|
||||
0xe1 0
|
||||
0xe2 0
|
||||
0xe3 0
|
||||
0xe4 0
|
||||
0xe5 0
|
||||
0xe6 0
|
||||
0xe7 0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fef08000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfef08000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
||||
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x18 0x2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x40000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,447 +0,0 @@
|
|||
/*
|
||||
* SBC8641D Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Wind River Systems Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SBC8641D";
|
||||
compatible = "wind,sbc8641";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>; // L1
|
||||
i-cache-size = <32768>; // L1
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; // 512M at 0x0
|
||||
};
|
||||
|
||||
localbus@f8005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
reg = <0xf8005000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
|
||||
1 0 0xf0000000 0x00010000 // 64KB EEPROM
|
||||
2 0 0xf1000000 0x00100000 // EPLD (1MB)
|
||||
3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
|
||||
4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
|
||||
6 0 0xf4000000 0x00100000 // LCD display (1MB)
|
||||
7 0 0xe8000000 0x04000000>; // 64MB OneNAND
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x01000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "dtb";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "fs";
|
||||
reg = <0x00500000 0x00a00000>;
|
||||
};
|
||||
partition@700000 {
|
||||
label = "firmware";
|
||||
reg = <0x00f00000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
epld@2,0 {
|
||||
compatible = "wrs,epld-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <2 0 0x100000>;
|
||||
ranges = <0 0 5 0 1 // User switches
|
||||
1 0 5 1 1 // Board ID/Rev
|
||||
3 0 5 3 1>; // LEDs
|
||||
};
|
||||
};
|
||||
|
||||
soc@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf8000000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
mcm-law@0 {
|
||||
compatible = "fsl,mcm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
mcm@1000 {
|
||||
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8641-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy2: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy3: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@f8008000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf8008000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0000 0 0 1 &mpic 0 1
|
||||
0x0000 0 0 2 &mpic 1 1
|
||||
0x0000 0 0 3 &mpic 2 1
|
||||
0x0000 0 0 4 &mpic 3 1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci1: pcie@f8009000 {
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf8009000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0x0000 0 0 1 &mpic 4 1
|
||||
0x0000 0 0 2 &mpic 5 1
|
||||
0x0000 0 0 3 &mpic 6 1
|
||||
0x0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -35,7 +35,6 @@ CONFIG_MTD_PHYSMAP=y
|
|||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_SPI_ATTRS=y
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ CONFIG_MTD_PHYSMAP_OF=y
|
|||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_IDE=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_FS_ENET=y
|
||||
# CONFIG_FS_ENET_HAS_SCC is not set
|
||||
|
|
|
|||
|
|
@ -31,8 +31,6 @@ CONFIG_BLK_DEV_LOOP=m
|
|||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=32768
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=m
|
||||
CONFIG_SCSI=m
|
||||
CONFIG_BLK_DEV_SD=m
|
||||
CONFIG_CHR_DEV_ST=m
|
||||
|
|
|
|||
|
|
@ -0,0 +1,104 @@
|
|||
CONFIG_ATA=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
# CONFIG_CARDBUS is not set
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_DS1682=y
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_GEF_WDT=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_GPIO_GE_FPGA=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_TULIP=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_PCCARD=y
|
||||
CONFIG_PCI_DEBUG=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCI=y
|
||||
# CONFIG_PCMCIA_LOAD_CIS is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_RTC_DRV_RX8581=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_SATA_SIL=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM92=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SND_INTEL8X0=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
CONFIG_SND_PCM_OSS=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
CONFIG_SND=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_ULI526X=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_VME_BUS=y
|
||||
CONFIG_VME_TSI148=y
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_YENTA_O2 is not set
|
||||
# CONFIG_YENTA_RICOH is not set
|
||||
# CONFIG_YENTA_TOSHIBA is not set
|
||||
CONFIG_YENTA=y
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SMP=y
|
||||
|
|
@ -1,216 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_GEF_PPC9A=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCCARD=y
|
||||
# CONFIG_PCMCIA_LOAD_CIS is not set
|
||||
# CONFIG_CARDBUS is not set
|
||||
CONFIG_YENTA=y
|
||||
# CONFIG_YENTA_O2 is not set
|
||||
# CONFIG_YENTA_RICOH is not set
|
||||
# CONFIG_YENTA_TOSHIBA is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_DS1682=y
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECS=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_SIL=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
CONFIG_SLIP=m
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_SMART=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_SERIAL_8250_PCI is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_GE_FPGA=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM92=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_GEF_WDT=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_INTF_PROC is not set
|
||||
CONFIG_RTC_DRV_RX8581=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_VME_BUS=y
|
||||
CONFIG_VME_TSI148=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_FAT_DEFAULT_CODEPAGE=850
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -1,214 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_GEF_SBC310=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCCARD=y
|
||||
# CONFIG_PCMCIA_LOAD_CIS is not set
|
||||
# CONFIG_CARDBUS is not set
|
||||
CONFIG_YENTA=y
|
||||
# CONFIG_YENTA_O2 is not set
|
||||
# CONFIG_YENTA_RICOH is not set
|
||||
# CONFIG_YENTA_TOSHIBA is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_DS1682=y
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECS=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
# CONFIG_ATA_SFF is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
CONFIG_SLIP=m
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_SMART=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_SERIAL_8250_PCI is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_GE_FPGA=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM92=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_GEF_WDT=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_INTF_PROC is not set
|
||||
CONFIG_RTC_DRV_RX8581=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_FAT_DEFAULT_CODEPAGE=850
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -1,273 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_GEF_SBC610=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCI_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_MATCH_ECN=m
|
||||
CONFIG_IP_NF_MATCH_TTL=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_TARGET_ECN=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_EUI64=m
|
||||
CONFIG_IP6_NF_MATCH_FRAG=m
|
||||
CONFIG_IP6_NF_MATCH_OPTS=m
|
||||
CONFIG_IP6_NF_MATCH_HL=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_MATCH_RT=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_RAW=m
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_TIPC=m
|
||||
CONFIG_ATM=m
|
||||
CONFIG_ATM_CLIP=m
|
||||
CONFIG_ATM_LANE=m
|
||||
CONFIG_ATM_MPOA=m
|
||||
CONFIG_ATM_BR2684=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_ATM=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_DS1682=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_SIL=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOATM=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
CONFIG_SLIP=m
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_SMART=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_SERIAL_8250_PCI is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_GE_FPGA=y
|
||||
CONFIG_SENSORS_LM90=y
|
||||
CONFIG_SENSORS_LM92=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_GEF_WDT=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_INTF_PROC is not set
|
||||
CONFIG_RTC_DRV_RX8581=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_VME_BUS=y
|
||||
CONFIG_VME_TSI148=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_ELF_CORE is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_LDM_PARTITION=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_MPC8610_HPCD=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_PCI_DEBUG=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_TULIP=y
|
||||
CONFIG_ULI526X=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_MPC=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_FSL_DIU=y
|
||||
CONFIG_VGACON_SOFT_SCROLLBACK=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
CONFIG_SND_PCM_OSS=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_POWERPC_SOC=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_MPC8641_HPCN=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_MPC=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
CONFIG_SND_PCM_OSS=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
CONFIG_SND_INTEL8X0=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_ADFS_FS=m
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_BEFS_FS=m
|
||||
CONFIG_BFS_FS=m
|
||||
CONFIG_EFS_FS=m
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_VXFS_FS=m
|
||||
CONFIG_HPFS_FS=m
|
||||
CONFIG_QNX4FS_FS=m
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -1,246 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_SBC8641D=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIEASPM is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_MATCH_ECN=m
|
||||
CONFIG_IP_NF_MATCH_TTL=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_TARGET_ECN=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_EUI64=m
|
||||
CONFIG_IP6_NF_MATCH_FRAG=m
|
||||
CONFIG_IP6_NF_MATCH_OPTS=m
|
||||
CONFIG_IP6_NF_MATCH_HL=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_MATCH_RT=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_RAW=m
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_TIPC=m
|
||||
CONFIG_ATM=m
|
||||
CONFIG_ATM_CLIP=m
|
||||
CONFIG_ATM_LANE=m
|
||||
CONFIG_ATM_MPOA=m
|
||||
CONFIG_ATM_BR2684=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_ATM=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_MD=y
|
||||
CONFIG_MD_LINEAR=y
|
||||
CONFIG_MD_RAID0=y
|
||||
CONFIG_MD_RAID1=y
|
||||
CONFIG_MD_RAID10=y
|
||||
CONFIG_MD_MULTIPATH=y
|
||||
CONFIG_MD_FAULTY=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_DM_SNAPSHOT=y
|
||||
CONFIG_DM_MIRROR=y
|
||||
CONFIG_DM_ZERO=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_BSDCOMP=m
|
||||
CONFIG_PPP_DEFLATE=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOATM=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_PPP_SYNC_TTY=m
|
||||
CONFIG_SLIP=m
|
||||
CONFIG_SLIP_COMPRESSED=y
|
||||
CONFIG_SLIP_SMART=y
|
||||
CONFIG_SLIP_MODE_SLIP6=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_SERIAL_8250_PCI is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MPC=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_SOFT_WATCHDOG=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_REISERFS_FS=m
|
||||
CONFIG_REISERFS_FS_XATTR=y
|
||||
CONFIG_REISERFS_FS_POSIX_ACL=y
|
||||
CONFIG_AUTOFS4_FS=m
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_MINIX_FS=m
|
||||
CONFIG_ROMFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
CONFIG_HIGHMEM=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_GEF_PPC9A=y
|
||||
CONFIG_GEF_SBC310=y
|
||||
CONFIG_GEF_SBC610=y
|
||||
CONFIG_MPC8610_HPCD=y
|
||||
CONFIG_MPC8641_HPCN=y
|
||||
CONFIG_SBC8641D=y
|
||||
|
|
@ -1,162 +0,0 @@
|
|||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
# CONFIG_PPC_CHRP is not set
|
||||
# CONFIG_PPC_PMAC is not set
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_MPC8641_HPCN=y
|
||||
CONFIG_SBC8641D=y
|
||||
CONFIG_MPC8610_HPCD=y
|
||||
CONFIG_GEF_SBC610=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IP_PNP_RARP=y
|
||||
CONFIG_NET_IPIP=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_ST=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_MPC=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_MIXER_OSS=y
|
||||
CONFIG_SND_PCM_OSS=y
|
||||
# CONFIG_SND_SUPPORT_OLD_API is not set
|
||||
CONFIG_SND_INTEL8X0=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GYRATION=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HID_PANTHERLORD=y
|
||||
CONFIG_HID_PETALYNX=y
|
||||
CONFIG_HID_SAMSUNG=y
|
||||
CONFIG_HID_SUNPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
|
||||
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_ADFS_FS=m
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_BEFS_FS=m
|
||||
CONFIG_BFS_FS=m
|
||||
CONFIG_EFS_FS=m
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_VXFS_FS=m
|
||||
CONFIG_HPFS_FS=m
|
||||
CONFIG_QNX4FS_FS=m
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
|
|
@ -69,6 +69,25 @@ extern void _set_L3CR(unsigned long);
|
|||
#define _set_L3CR(val) do { } while(0)
|
||||
#endif
|
||||
|
||||
static inline void dcbz(void *addr)
|
||||
{
|
||||
__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void dcbi(void *addr)
|
||||
{
|
||||
__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void dcbf(void *addr)
|
||||
{
|
||||
__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void dcbst(void *addr)
|
||||
{
|
||||
__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
|
||||
}
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_CACHE_H */
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@ extern void flush_dcache_page(struct page *page);
|
|||
#define flush_dcache_mmap_lock(mapping) do { } while (0)
|
||||
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
|
||||
|
||||
extern void __flush_disable_L1(void);
|
||||
|
||||
extern void flush_icache_range(unsigned long, unsigned long);
|
||||
extern void flush_icache_user_range(struct vm_area_struct *vma,
|
||||
struct page *page, unsigned long addr,
|
||||
|
|
@ -47,12 +45,58 @@ static inline void __flush_dcache_icache_phys(unsigned long physaddr)
|
|||
}
|
||||
#endif
|
||||
|
||||
extern void flush_dcache_range(unsigned long start, unsigned long stop);
|
||||
#ifdef CONFIG_PPC32
|
||||
extern void clean_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
|
||||
/*
|
||||
* Write any modified data cache blocks out to memory and invalidate them.
|
||||
* Does not invalidate the corresponding instruction cache blocks.
|
||||
*/
|
||||
static inline void flush_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
|
||||
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
|
||||
dcbf(addr);
|
||||
mb(); /* sync */
|
||||
}
|
||||
|
||||
/*
|
||||
* Write any modified data cache blocks out to memory.
|
||||
* Does not invalidate the corresponding cache lines (especially for
|
||||
* any corresponding instruction cache).
|
||||
*/
|
||||
static inline void clean_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
|
||||
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
|
||||
dcbst(addr);
|
||||
mb(); /* sync */
|
||||
}
|
||||
|
||||
/*
|
||||
* Like above, but invalidate the D-cache. This is used by the 8xx
|
||||
* to invalidate the cache so the PPC core doesn't get stale data
|
||||
* from the CPM (no cache snooping here :-).
|
||||
*/
|
||||
static inline void invalidate_dcache_range(unsigned long start,
|
||||
unsigned long stop)
|
||||
{
|
||||
void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1));
|
||||
unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1);
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < size >> L1_CACHE_SHIFT; i++, addr += L1_CACHE_BYTES)
|
||||
dcbi(addr);
|
||||
mb(); /* sync */
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PPC32 */
|
||||
#ifdef CONFIG_PPC64
|
||||
extern void flush_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
|
||||
extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,30 +9,9 @@
|
|||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is a version of ip_compute_csum() optimized for IP headers,
|
||||
* which always checksum on 4 octet boundaries. ihl is the number
|
||||
* of 32-bit words and is always >= 5.
|
||||
*/
|
||||
#ifdef CONFIG_GENERIC_CSUM
|
||||
#include <asm-generic/checksum.h>
|
||||
#else
|
||||
extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
|
||||
|
||||
/*
|
||||
* computes the checksum of a memory block at buff, length len,
|
||||
* and adds in "sum" (32-bit)
|
||||
*
|
||||
* returns a 32-bit number suitable for feeding into itself
|
||||
* or csum_tcpudp_magic
|
||||
*
|
||||
* this function must be called with even lengths, except
|
||||
* for the last fragment, which may be odd
|
||||
*
|
||||
* it's best to have buff aligned on a 32-bit boundary
|
||||
*/
|
||||
extern __wsum csum_partial(const void *buff, int len, __wsum sum);
|
||||
|
||||
/*
|
||||
* Computes the checksum of a memory block at src, length len,
|
||||
* and adds in "sum" (32-bit), while copying the block to dst.
|
||||
|
|
@ -47,21 +26,12 @@ extern __wsum csum_partial_copy_generic(const void *src, void *dst,
|
|||
int len, __wsum sum,
|
||||
int *src_err, int *dst_err);
|
||||
|
||||
#ifdef __powerpc64__
|
||||
#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
|
||||
extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
|
||||
int len, __wsum sum, int *err_ptr);
|
||||
#define HAVE_CSUM_COPY_USER
|
||||
extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
|
||||
int len, __wsum sum, int *err_ptr);
|
||||
#else
|
||||
/*
|
||||
* the same as csum_partial, but copies from src to dst while it
|
||||
* checksums.
|
||||
*/
|
||||
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
|
||||
csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
|
||||
#endif
|
||||
|
||||
#define csum_partial_copy_nocheck(src, dst, len, sum) \
|
||||
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
|
||||
|
|
@ -83,15 +53,6 @@ static inline __sum16 csum_fold(__wsum sum)
|
|||
return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
|
||||
}
|
||||
|
||||
/*
|
||||
* this routine is used for miscellaneous IP-like checksums, mainly
|
||||
* in icmp.c
|
||||
*/
|
||||
static inline __sum16 ip_compute_csum(const void *buff, int len)
|
||||
{
|
||||
return csum_fold(csum_partial(buff, len, 0));
|
||||
}
|
||||
|
||||
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
|
||||
unsigned short len,
|
||||
unsigned short proto,
|
||||
|
|
@ -135,17 +96,117 @@ static inline __wsum csum_add(__wsum csum, __wsum addend)
|
|||
{
|
||||
#ifdef __powerpc64__
|
||||
u64 res = (__force u64)csum;
|
||||
#endif
|
||||
if (__builtin_constant_p(csum) && csum == 0)
|
||||
return addend;
|
||||
if (__builtin_constant_p(addend) && addend == 0)
|
||||
return csum;
|
||||
|
||||
#ifdef __powerpc64__
|
||||
res += (__force u64)addend;
|
||||
return (__force __wsum)((u32)res + (res >> 32));
|
||||
#else
|
||||
asm("addc %0,%0,%1;"
|
||||
"addze %0,%0;"
|
||||
: "+r" (csum) : "r" (addend));
|
||||
: "+r" (csum) : "r" (addend) : "xer");
|
||||
return csum;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* This is a version of ip_compute_csum() optimized for IP headers,
|
||||
* which always checksum on 4 octet boundaries. ihl is the number
|
||||
* of 32-bit words and is always >= 5.
|
||||
*/
|
||||
static inline __wsum ip_fast_csum_nofold(const void *iph, unsigned int ihl)
|
||||
{
|
||||
const u32 *ptr = (const u32 *)iph + 1;
|
||||
#ifdef __powerpc64__
|
||||
unsigned int i;
|
||||
u64 s = *(const u32 *)iph;
|
||||
|
||||
for (i = 0; i < ihl - 1; i++, ptr++)
|
||||
s += *ptr;
|
||||
s += (s >> 32);
|
||||
return (__force __wsum)s;
|
||||
#else
|
||||
__wsum sum, tmp;
|
||||
|
||||
asm("mtctr %3;"
|
||||
"addc %0,%4,%5;"
|
||||
"1: lwzu %1, 4(%2);"
|
||||
"adde %0,%0,%1;"
|
||||
"bdnz 1b;"
|
||||
"addze %0,%0;"
|
||||
: "=r" (sum), "=r" (tmp), "+b" (ptr)
|
||||
: "r" (ihl - 2), "r" (*(const u32 *)iph), "r" (*ptr)
|
||||
: "ctr", "xer", "memory");
|
||||
|
||||
return sum;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
|
||||
{
|
||||
return csum_fold(ip_fast_csum_nofold(iph, ihl));
|
||||
}
|
||||
|
||||
/*
|
||||
* computes the checksum of a memory block at buff, length len,
|
||||
* and adds in "sum" (32-bit)
|
||||
*
|
||||
* returns a 32-bit number suitable for feeding into itself
|
||||
* or csum_tcpudp_magic
|
||||
*
|
||||
* this function must be called with even lengths, except
|
||||
* for the last fragment, which may be odd
|
||||
*
|
||||
* it's best to have buff aligned on a 32-bit boundary
|
||||
*/
|
||||
__wsum __csum_partial(const void *buff, int len, __wsum sum);
|
||||
|
||||
static inline __wsum csum_partial(const void *buff, int len, __wsum sum)
|
||||
{
|
||||
if (__builtin_constant_p(len) && len <= 16 && (len & 1) == 0) {
|
||||
if (len == 2)
|
||||
sum = csum_add(sum, (__force __wsum)*(const u16 *)buff);
|
||||
if (len >= 4)
|
||||
sum = csum_add(sum, (__force __wsum)*(const u32 *)buff);
|
||||
if (len == 6)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u16 *)(buff + 4));
|
||||
if (len >= 8)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u32 *)(buff + 4));
|
||||
if (len == 10)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u16 *)(buff + 8));
|
||||
if (len >= 12)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u32 *)(buff + 8));
|
||||
if (len == 14)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u16 *)(buff + 12));
|
||||
if (len >= 16)
|
||||
sum = csum_add(sum, (__force __wsum)
|
||||
*(const u32 *)(buff + 12));
|
||||
} else if (__builtin_constant_p(len) && (len & 3) == 0) {
|
||||
sum = csum_add(sum, ip_fast_csum_nofold(buff, len >> 2));
|
||||
} else {
|
||||
sum = __csum_partial(buff, len, sum);
|
||||
}
|
||||
return sum;
|
||||
}
|
||||
|
||||
/*
|
||||
* this routine is used for miscellaneous IP-like checksums, mainly
|
||||
* in icmp.c
|
||||
*/
|
||||
static inline __sum16 ip_compute_csum(const void *buff, int len)
|
||||
{
|
||||
return csum_fold(csum_partial(buff, len, 0));
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* __KERNEL__ */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -43,6 +43,11 @@ extern int machine_check_e500(struct pt_regs *regs);
|
|||
extern int machine_check_e200(struct pt_regs *regs);
|
||||
extern int machine_check_47x(struct pt_regs *regs);
|
||||
|
||||
extern void cpu_down_flush_e500v2(void);
|
||||
extern void cpu_down_flush_e500mc(void);
|
||||
extern void cpu_down_flush_e5500(void);
|
||||
extern void cpu_down_flush_e6500(void);
|
||||
|
||||
/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
|
||||
struct cpu_spec {
|
||||
/* CPU is matched via (PVR & pvr_mask) == pvr_value */
|
||||
|
|
@ -59,6 +64,9 @@ struct cpu_spec {
|
|||
unsigned int icache_bsize;
|
||||
unsigned int dcache_bsize;
|
||||
|
||||
/* flush caches inside the current cpu */
|
||||
void (*cpu_down_flush)(void);
|
||||
|
||||
/* number of performance monitor counters */
|
||||
unsigned int num_pmcs;
|
||||
enum powerpc_pmc_type pmc_type;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef _ASM_POWERPC_CPUTHREADS_H
|
||||
#define _ASM_POWERPC_CPUTHREADS_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/cpumask.h>
|
||||
|
||||
/*
|
||||
|
|
@ -94,7 +95,21 @@ static inline int cpu_last_thread_sibling(int cpu)
|
|||
return cpu | (threads_per_core - 1);
|
||||
}
|
||||
|
||||
static inline u32 get_tensr(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOKE
|
||||
if (cpu_has_feature(CPU_FTR_SMT))
|
||||
return mfspr(SPRN_TENSR);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
void book3e_start_thread(int thread, unsigned long addr);
|
||||
void book3e_stop_thread(int thread);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define INVALID_THREAD_HWID 0x0fff
|
||||
|
||||
#endif /* _ASM_POWERPC_CPUTHREADS_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Support Power Management
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __PPC_FSL_PM_H
|
||||
#define __PPC_FSL_PM_H
|
||||
|
||||
#define E500_PM_PH10 1
|
||||
#define E500_PM_PH15 2
|
||||
#define E500_PM_PH20 3
|
||||
#define E500_PM_PH30 4
|
||||
#define E500_PM_DOZE E500_PM_PH10
|
||||
#define E500_PM_NAP E500_PM_PH15
|
||||
|
||||
#define PLAT_PM_SLEEP 20
|
||||
#define PLAT_PM_LPM20 30
|
||||
|
||||
#define FSL_PM_SLEEP (1 << 0)
|
||||
#define FSL_PM_DEEP_SLEEP (1 << 1)
|
||||
|
||||
struct fsl_pm_ops {
|
||||
/* mask pending interrupts to the RCPM from MPIC */
|
||||
void (*irq_mask)(int cpu);
|
||||
|
||||
/* unmask pending interrupts to the RCPM from MPIC */
|
||||
void (*irq_unmask)(int cpu);
|
||||
void (*cpu_enter_state)(int cpu, int state);
|
||||
void (*cpu_exit_state)(int cpu, int state);
|
||||
void (*cpu_up_prepare)(int cpu);
|
||||
void (*cpu_die)(int cpu);
|
||||
int (*plat_enter_sleep)(void);
|
||||
void (*freeze_time_base)(bool freeze);
|
||||
|
||||
/* keep the power of IP blocks during sleep/deep sleep */
|
||||
void (*set_ip_power)(bool enable, u32 mask);
|
||||
|
||||
/* get platform supported power management modes */
|
||||
unsigned int (*get_pm_modes)(void);
|
||||
};
|
||||
|
||||
extern const struct fsl_pm_ops *qoriq_pm_ops;
|
||||
|
||||
int __init fsl_rcpm_init(void);
|
||||
|
||||
#endif /* __PPC_FSL_PM_H */
|
||||
|
|
@ -171,9 +171,9 @@ typedef struct {
|
|||
} mm_context_t;
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#if (PAGE_SHIFT == 12)
|
||||
#if defined(CONFIG_PPC_4K_PAGES)
|
||||
#define mmu_virtual_psize MMU_PAGE_4K
|
||||
#elif (PAGE_SHIFT == 14)
|
||||
#elif defined(CONFIG_PPC_16K_PAGES)
|
||||
#define mmu_virtual_psize MMU_PAGE_16K
|
||||
#else
|
||||
#error "Unsupported PAGE_SIZE"
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ extern int icache_44x_need_flush;
|
|||
* We no longer map larger than phys RAM with the BATs so we don't have
|
||||
* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
|
||||
* about clashes between our early calls to ioremap() that start growing down
|
||||
* from ioremap_base being run into the VM area allocations (growing upwards
|
||||
* from IOREMAP_TOP being run into the VM area allocations (growing upwards
|
||||
* from VMALLOC_START). For this reason we have ioremap_bot to check when
|
||||
* we actually run into our mappings setup in the early boot with the VM
|
||||
* system. This really does become a problem for machines with good amounts
|
||||
|
|
@ -309,7 +309,8 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
|
|||
#define pte_index(address) \
|
||||
(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
||||
#define pte_offset_kernel(dir, addr) \
|
||||
((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
|
||||
(pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \
|
||||
pte_index(addr))
|
||||
#define pte_offset_map(dir, addr) \
|
||||
((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
|
||||
#define pte_unmap(pte) kunmap_atomic(pte)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
#ifndef _ASM_POWERPC_PAGE_32_H
|
||||
#define _ASM_POWERPC_PAGE_32_H
|
||||
|
||||
#include <asm/cache.h>
|
||||
|
||||
#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
|
||||
#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
|
||||
#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
|
||||
|
|
@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t;
|
|||
typedef unsigned long pte_basic_t;
|
||||
#endif
|
||||
|
||||
struct page;
|
||||
extern void clear_pages(void *page, int order);
|
||||
static inline void clear_page(void *page) { clear_pages(page, 0); }
|
||||
/*
|
||||
* Clear page using the dcbz instruction, which doesn't cause any
|
||||
* memory traffic (except to write out any cache lines which get
|
||||
* displaced). This only works on cacheable memory.
|
||||
*/
|
||||
static inline void clear_page(void *addr)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
|
||||
dcbz(addr);
|
||||
}
|
||||
extern void copy_page(void *to, void *from);
|
||||
|
||||
#include <asm-generic/getorder.h>
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue