libata: support AHCI on OCTEON platform
The OCTEON SATA controller is currently found on cn71XX devices. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Vinita Gupta <vgupta@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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@ -11,6 +11,7 @@ Required properties:
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- compatible : compatible string, one of:
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- "allwinner,sun4i-a10-ahci"
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- "hisilicon,hisi-ahci"
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- "cavium,octeon-7130-ahci"
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- "ibm,476gtr-ahci"
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- "marvell,armada-380-ahci"
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- "snps,dwc-ahci"
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42
Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
Normal file
42
Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
Normal file
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@ -0,0 +1,42 @@
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* UCTL SATA controller glue
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UCTL is the bridge unit between the I/O interconnect (an internal bus)
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and the SATA AHCI host controller (UAHC). It performs the following functions:
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- provides interfaces for the applications to access the UAHC AHCI
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registers on the CN71XX I/O space.
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- provides a bridge for UAHC to fetch AHCI command table entries and data
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buffers from Level 2 Cache.
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- posts interrupts to the CIU.
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- contains registers that:
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- control the behavior of the UAHC
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- control the clock/reset generation to UAHC
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- control endian swapping for all UAHC registers and DMA accesses
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Properties:
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- compatible: "cavium,octeon-7130-sata-uctl"
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Compatibility with the cn7130 SOC.
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- reg: The base address of the UCTL register bank.
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- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
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suitable values to map all child nodes.
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Example:
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uctl@118006c000000 {
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compatible = "cavium,octeon-7130-sata-uctl";
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reg = <0x11800 0x6c000000 0x0 0x100>;
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ranges; /* Direct mapping */
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dma-ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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sata: sata@16c0000000000 {
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compatible = "cavium,octeon-7130-ahci";
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reg = <0x16c00 0x00000000 0x0 0x200>;
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interrupt-parent = <&cibsata>;
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interrupts = <2 4>; /* Bit: 2, level */
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};
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};
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@ -275,6 +275,11 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
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cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
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}
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static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
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{
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cvmx_write_csr((__force uint64_t)csr_addr, val);
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}
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static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
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{
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cvmx_write64(io_addr, val);
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@ -287,6 +292,10 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
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return val;
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}
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static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
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{
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return cvmx_read_csr((__force uint64_t) csr_addr);
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}
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static inline void cvmx_send_single(uint64_t data)
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{
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@ -151,6 +151,15 @@ config AHCI_MVEBU
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If unsure, say N.
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config AHCI_OCTEON
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tristate "Cavium Octeon Soc Serial ATA"
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depends on SATA_AHCI_PLATFORM && CAVIUM_OCTEON_SOC
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default y
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help
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This option enables support for Cavium Octeon SoC Serial ATA.
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If unsure, say N.
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config AHCI_SUNXI
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tristate "Allwinner sunxi AHCI SATA support"
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depends on ARCH_SUNXI
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@ -15,6 +15,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
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obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_TEGRA) += ahci_tegra.o libahci.o libahci_platform.o
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105
drivers/ata/ahci_octeon.c
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105
drivers/ata/ahci_octeon.c
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/*
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* SATA glue for Cavium Octeon III SOCs.
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2010-2015 Cavium Networks
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*
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <asm/octeon/octeon.h>
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#include <asm/bitfield.h>
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#define CVMX_SATA_UCTL_SHIM_CFG 0xE8
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#define SATA_UCTL_ENDIAN_MODE_BIG 1
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#define SATA_UCTL_ENDIAN_MODE_LITTLE 0
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#define SATA_UCTL_ENDIAN_MODE_MASK 3
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#define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
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#define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
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#define SATA_UCTL_DMA_READ_CMD_SHIFT 12
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static int ahci_octeon_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct resource *res;
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void __iomem *base;
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u64 cfg;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "Platform resource[0] is missing\n");
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return -ENODEV;
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}
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
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cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
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cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
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#ifdef __BIG_ENDIAN
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cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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#else
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cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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#endif
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cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
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cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
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if (!node) {
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dev_err(dev, "no device node, failed to add octeon sata\n");
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return -ENODEV;
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}
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ret = of_platform_populate(node, NULL, NULL, dev);
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if (ret) {
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dev_err(dev, "failed to add ahci-platform core\n");
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return ret;
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}
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return 0;
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}
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static int ahci_octeon_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id octeon_ahci_match[] = {
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{ .compatible = "cavium,octeon-7130-sata-uctl", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_ahci_match);
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static struct platform_driver ahci_octeon_driver = {
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.probe = ahci_octeon_probe,
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.remove = ahci_octeon_remove,
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.driver = {
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.name = "octeon-ahci",
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.of_match_table = octeon_ahci_match,
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},
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};
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module_platform_driver(ahci_octeon_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
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MODULE_DESCRIPTION("Cavium Inc. sata config.");
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@ -76,6 +76,7 @@ static const struct of_device_id ahci_of_match[] = {
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{ .compatible = "ibm,476gtr-ahci", },
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{ .compatible = "snps,dwc-ahci", },
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{ .compatible = "hisilicon,hisi-ahci", },
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{ .compatible = "cavium,octeon-7130-ahci", },
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_of_match);
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