[PATCH] fbdev driver for S3 Trio/Virge
Add a driver for S3 Trio / S3 Virge. Driver is tested with most versions of S3 Trio and with S3 Virge/DX, on i386. (akpm: We kind-of have support for this hardware already, but... virgefb.c - amiga/zorro specific, - broken (according to Kconfig), - uses obsolete/nonexistent interface (struct display_switch) - recent Adrian Bunk's patch removes this driver S3triofb.c - ppc/openfirmware specific - minimal functionality - broken (according to Kconfig), - uses obsolete/nonexistent interface (struct display_switch) ) Signed-off-by: Ondrej Zajicek <santiago@crfreenet.org> Cc: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>hifive-unleashed-5.1
Ondrej Zajicek
Linus Torvalds
parent
59ae6c6b87
commit
a268422de8
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@ -0,0 +1,78 @@
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s3fb - fbdev driver for S3 Trio/Virge chips
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===========================================
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Supported Hardware
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==================
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S3 Trio32
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S3 Trio64 (and variants V+, UV+, V2/DX, V2/GX)
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S3 Virge (and variants VX, DX, GX and GX2+)
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S3 Plato/PX (completely untested)
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S3 Aurora64V+ (completely untested)
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- only PCI bus supported
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- only BIOS initialized VGA devices supported
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- probably not working on big endian
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I tested s3fb on Trio64 (plain, V+ and V2/DX) and Virge (plain, VX, DX),
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all on i386.
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Supported Features
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==================
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* 4 bpp pseudocolor modes (with 18bit palette, two variants)
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* 8 bpp pseudocolor mode (with 18bit palette)
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* 16 bpp truecolor modes (RGB 555 and RGB 565)
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* 24 bpp truecolor mode (RGB 888) on (only on Virge VX)
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* 32 bpp truecolor mode (RGB 888) on (not on Virge VX)
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* text mode (activated by bpp = 0)
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* interlaced mode variant (not available in text mode)
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* doublescan mode variant (not available in text mode)
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* panning in both directions
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* suspend/resume support
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* DPMS support
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Text mode is supported even in higher resolutions, but there is limitation
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to lower pixclocks (maximum between 50-60 MHz, depending on specific hardware).
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This limitation is not enforced by driver. Text mode supports 8bit wide fonts
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only (hardware limitation) and 16bit tall fonts (driver limitation).
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There are two 4 bpp modes. First mode (selected if nonstd == 0) is mode with
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packed pixels, high nibble first. Second mode (selected if nonstd == 1) is mode
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with interleaved planes (1 byte interleave), MSB first. Both modes support
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8bit wide fonts only (driver limitation).
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Suspend/resume works on systems that initialize video card during resume and
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if device is active (for example used by fbcon).
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Missing Features
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================
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(alias TODO list)
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* secondary (not initialized by BIOS) device support
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* big endian support
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* Zorro bus support
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* MMIO support
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* 24 bpp mode support on more cards
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* support for fontwidths != 8 in 4 bpp modes
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* support for fontheight != 16 in text mode
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* composite and external sync (is anyone able to test this?)
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* hardware cursor
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* video overlay support
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* vsync synchronization
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* feature connector support
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* acceleration support (8514-like 2D, Virge 3D, busmaster transfers)
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* better values for some magic registers (performance issues)
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Known bugs
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==========
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* cursor disable in text mode doesn't work
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--
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Ondrej Zajicek <santiago@crfreenet.org>
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@ -85,6 +85,14 @@ config FB_CFB_IMAGEBLIT
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blitting. This is used by drivers that don't provide their own
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(accelerated) version.
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config FB_SVGALIB
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tristate
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depends on FB
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default n
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---help---
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Common utility functions useful to fbdev drivers of VGA-based
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cards.
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config FB_MACMODES
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tristate
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depends on FB
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@ -1147,6 +1155,17 @@ config FB_S3TRIO
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help
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If you have a S3 Trio say Y. Say N for S3 Virge.
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config FB_S3
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tristate "S3 Trio/Virge support"
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depends on FB && PCI
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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select FB_TILEBLITTING
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select FB_SVGALIB
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---help---
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Driver for graphics boards with S3 Trio / S3 Virge chip.
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config FB_SAVAGE
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tristate "S3 Savage support"
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depends on FB && PCI && EXPERIMENTAL
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@ -17,6 +17,7 @@ obj-$(CONFIG_SYSFS) += backlight/
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obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o
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obj-$(CONFIG_FB_CFB_COPYAREA) += cfbcopyarea.o
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obj-$(CONFIG_FB_CFB_IMAGEBLIT) += cfbimgblt.o
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obj-$(CONFIG_FB_SVGALIB) += svgalib.o
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obj-$(CONFIG_FB_MACMODES) += macmodes.o
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obj-$(CONFIG_FB_DDC) += fb_ddc.o
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@ -54,6 +55,7 @@ obj-$(CONFIG_FB_S3TRIO) += S3triofb.o
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obj-$(CONFIG_FB_FM2) += fm2fb.o
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obj-$(CONFIG_FB_CYBLA) += cyblafb.o
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obj-$(CONFIG_FB_TRIDENT) += tridentfb.o
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obj-$(CONFIG_FB_S3) += s3fb.o vgastate.o
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obj-$(CONFIG_FB_STI) += stifb.o
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obj-$(CONFIG_FB_FFB) += ffb.o sbuslib.o
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obj-$(CONFIG_FB_CG6) += cg6.o sbuslib.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,632 @@
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/*
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* Common utility functions for VGA-based graphics cards.
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*
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* Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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* Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/fb.h>
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#include <linux/svga.h>
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#include <linux/slab.h>
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#include <asm/types.h>
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#include <asm/io.h>
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/* Write a CRT register value spread across multiple registers */
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void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
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u8 regval, bitval, bitnum;
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while (regset->regnum != VGA_REGSET_END_VAL) {
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regval = vga_rcrt(NULL, regset->regnum);
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bitnum = regset->lowbit;
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while (bitnum <= regset->highbit) {
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bitval = 1 << bitnum;
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regval = regval & ~bitval;
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if (value & 1) regval = regval | bitval;
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bitnum ++;
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value = value >> 1;
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}
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vga_wcrt(NULL, regset->regnum, regval);
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regset ++;
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}
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}
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/* Write a sequencer register value spread across multiple registers */
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void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
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u8 regval, bitval, bitnum;
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while (regset->regnum != VGA_REGSET_END_VAL) {
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regval = vga_rseq(NULL, regset->regnum);
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bitnum = regset->lowbit;
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while (bitnum <= regset->highbit) {
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bitval = 1 << bitnum;
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regval = regval & ~bitval;
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if (value & 1) regval = regval | bitval;
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bitnum ++;
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value = value >> 1;
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}
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vga_wseq(NULL, regset->regnum, regval);
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regset ++;
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}
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}
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static unsigned int svga_regset_size(const struct vga_regset *regset)
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{
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u8 count = 0;
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while (regset->regnum != VGA_REGSET_END_VAL) {
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count += regset->highbit - regset->lowbit + 1;
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regset ++;
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}
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return 1 << count;
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}
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/* ------------------------------------------------------------------------- */
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/* Set graphics controller registers to sane values */
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void svga_set_default_gfx_regs(void)
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{
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/* All standard GFX registers (GR00 - GR08) */
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vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00);
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vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00);
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vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00);
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vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00);
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vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00);
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vga_wgfx(NULL, VGA_GFX_MODE, 0x00);
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/* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */
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/* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */
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vga_wgfx(NULL, VGA_GFX_MISC, 0x05);
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/* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */
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vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F);
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vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF);
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}
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/* Set attribute controller registers to sane values */
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void svga_set_default_atc_regs(void)
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{
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u8 count;
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vga_r(NULL, 0x3DA);
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vga_w(NULL, VGA_ATT_W, 0x00);
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/* All standard ATC registers (AR00 - AR14) */
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for (count = 0; count <= 0xF; count ++)
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svga_wattr(count, count);
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svga_wattr(VGA_ATC_MODE, 0x01);
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/* svga_wattr(VGA_ATC_MODE, 0x41); */
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svga_wattr(VGA_ATC_OVERSCAN, 0x00);
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svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F);
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svga_wattr(VGA_ATC_PEL, 0x00);
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svga_wattr(VGA_ATC_COLOR_PAGE, 0x00);
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vga_r(NULL, 0x3DA);
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vga_w(NULL, VGA_ATT_W, 0x20);
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}
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/* Set sequencer registers to sane values */
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void svga_set_default_seq_regs(void)
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{
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/* Standard sequencer registers (SR01 - SR04), SR00 is not set */
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vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
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vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
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vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00);
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/* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
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vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
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}
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/* Set CRTC registers to sane values */
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void svga_set_default_crt_regs(void)
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{
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/* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
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svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
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vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0);
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svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F);
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vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0);
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vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3);
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}
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void svga_set_textmode_vga_regs(void)
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{
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/* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
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vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
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vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03);
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vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
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vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f);
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svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f);
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vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d);
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vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e);
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vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00);
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vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00);
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vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
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vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
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vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00);
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vga_r(NULL, 0x3DA);
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vga_w(NULL, VGA_ATT_W, 0x00);
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svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
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svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */
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vga_r(NULL, 0x3DA);
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vga_w(NULL, VGA_ATT_W, 0x20);
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}
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#if 0
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void svga_dump_var(struct fb_var_screeninfo *var, int node)
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{
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pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
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pr_debug("fb%d: var.xres : %d\n", node, var->xres);
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pr_debug("fb%d: var.yres : %d\n", node, var->yres);
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pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
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pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
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pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
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pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
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pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
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pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
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pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
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pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
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pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
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pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
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pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
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}
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#endif /* 0 */
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/* ------------------------------------------------------------------------- */
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void svga_settile(struct fb_info *info, struct fb_tilemap *map)
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{
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const u8 *font = map->data;
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u8* fb = (u8 *) info->screen_base;
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int i, c;
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if ((map->width != 8) || (map->height != 16) ||
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(map->depth != 1) || (map->length != 256)) {
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printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
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info->node, map->width, map->height, map->depth, map->length);
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return;
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}
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fb += 2;
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for (c = 0; c < map->length; c++) {
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for (i = 0; i < map->height; i++) {
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fb[i * 4] = font[i];
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}
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fb += 128;
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font += map->height;
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}
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}
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/* Copy area in text (tileblit) mode */
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void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
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{
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int dx, dy;
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/* colstride is halved in this function because u16 are used */
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int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
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int rowstride = colstride * (info->var.xres_virtual / 8);
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u16 *fb = (u16 *) info->screen_base;
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u16 *src, *dst;
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if ((area->sy > area->dy) ||
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((area->sy == area->dy) && (area->sx > area->dx))) {
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src = fb + area->sx * colstride + area->sy * rowstride;
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dst = fb + area->dx * colstride + area->dy * rowstride;
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} else {
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src = fb + (area->sx + area->width - 1) * colstride
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+ (area->sy + area->height - 1) * rowstride;
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dst = fb + (area->dx + area->width - 1) * colstride
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+ (area->dy + area->height - 1) * rowstride;
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colstride = -colstride;
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rowstride = -rowstride;
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}
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for (dy = 0; dy < area->height; dy++) {
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u16* src2 = src;
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u16* dst2 = dst;
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for (dx = 0; dx < area->width; dx++) {
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*dst2 = *src2;
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src2 += colstride;
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dst2 += colstride;
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}
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src += rowstride;
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dst += rowstride;
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}
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}
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/* Fill area in text (tileblit) mode */
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void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
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{
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int dx, dy;
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int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
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int rowstride = colstride * (info->var.xres_virtual / 8);
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int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
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u8 *fb = (u8 *) info->screen_base;
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fb += rect->sx * colstride + rect->sy * rowstride;
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for (dy = 0; dy < rect->height; dy++) {
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u8* fb2 = fb;
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for (dx = 0; dx < rect->width; dx++) {
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fb2[0] = rect->index;
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fb2[1] = attr;
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fb2 += colstride;
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}
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fb += rowstride;
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}
|
||||
}
|
||||
|
||||
/* Write text in text (tileblit) mode */
|
||||
void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
|
||||
{
|
||||
int dx, dy, i;
|
||||
int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
|
||||
int rowstride = colstride * (info->var.xres_virtual / 8);
|
||||
int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
|
||||
u8* fb = (u8 *) info->screen_base;
|
||||
fb += blit->sx * colstride + blit->sy * rowstride;
|
||||
|
||||
i=0;
|
||||
for (dy=0; dy < blit->height; dy ++) {
|
||||
u8* fb2 = fb;
|
||||
for (dx = 0; dx < blit->width; dx ++) {
|
||||
fb2[0] = blit->indices[i];
|
||||
fb2[1] = attr;
|
||||
fb2 += colstride;
|
||||
i ++;
|
||||
if (i == blit->length) return;
|
||||
}
|
||||
fb += rowstride;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Set cursor in text (tileblit) mode */
|
||||
void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
|
||||
{
|
||||
u8 cs = 0x0d;
|
||||
u8 ce = 0x0e;
|
||||
u16 pos = cursor->sx + (info->var.xoffset / 8)
|
||||
+ (cursor->sy + (info->var.yoffset / 16))
|
||||
* (info->var.xres_virtual / 8);
|
||||
|
||||
if (! cursor -> mode)
|
||||
return;
|
||||
|
||||
svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */
|
||||
|
||||
if (cursor -> shape == FB_TILE_CURSOR_NONE)
|
||||
return;
|
||||
|
||||
switch (cursor -> shape) {
|
||||
case FB_TILE_CURSOR_UNDERLINE:
|
||||
cs = 0x0d;
|
||||
break;
|
||||
case FB_TILE_CURSOR_LOWER_THIRD:
|
||||
cs = 0x09;
|
||||
break;
|
||||
case FB_TILE_CURSOR_LOWER_HALF:
|
||||
cs = 0x07;
|
||||
break;
|
||||
case FB_TILE_CURSOR_TWO_THIRDS:
|
||||
cs = 0x05;
|
||||
break;
|
||||
case FB_TILE_CURSOR_BLOCK:
|
||||
cs = 0x01;
|
||||
break;
|
||||
}
|
||||
|
||||
/* set cursor position */
|
||||
vga_wcrt(NULL, 0x0E, pos >> 8);
|
||||
vga_wcrt(NULL, 0x0F, pos & 0xFF);
|
||||
|
||||
vga_wcrt(NULL, 0x0B, ce); /* set cursor end */
|
||||
vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Compute PLL settings (M, N, R)
|
||||
* F_VCO = (F_BASE * M) / N
|
||||
* F_OUT = F_VCO / (2^R)
|
||||
*/
|
||||
|
||||
static inline u32 abs_diff(u32 a, u32 b)
|
||||
{
|
||||
return (a > b) ? (a - b) : (b - a);
|
||||
}
|
||||
|
||||
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
|
||||
{
|
||||
u16 am, an, ar;
|
||||
u32 f_vco, f_current, delta_current, delta_best;
|
||||
|
||||
pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
|
||||
|
||||
ar = pll->r_max;
|
||||
f_vco = f_wanted << ar;
|
||||
|
||||
/* overflow check */
|
||||
if ((f_vco >> ar) != f_wanted)
|
||||
return -EINVAL;
|
||||
|
||||
/* It is usually better to have greater VCO clock
|
||||
because of better frequency stability.
|
||||
So first try r_max, then r smaller. */
|
||||
while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
|
||||
ar--;
|
||||
f_vco = f_vco >> 1;
|
||||
}
|
||||
|
||||
/* VCO bounds check */
|
||||
if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
|
||||
return -EINVAL;
|
||||
|
||||
delta_best = 0xFFFFFFFF;
|
||||
*m = 0;
|
||||
*n = 0;
|
||||
*r = ar;
|
||||
|
||||
am = pll->m_min;
|
||||
an = pll->n_min;
|
||||
|
||||
while ((am <= pll->m_max) && (an <= pll->n_max)) {
|
||||
f_current = (pll->f_base * am) / an;
|
||||
delta_current = abs_diff (f_current, f_vco);
|
||||
|
||||
if (delta_current < delta_best) {
|
||||
delta_best = delta_current;
|
||||
*m = am;
|
||||
*n = an;
|
||||
}
|
||||
|
||||
if (f_current <= f_vco) {
|
||||
am ++;
|
||||
} else {
|
||||
an ++;
|
||||
}
|
||||
}
|
||||
|
||||
f_current = (pll->f_base * *m) / *n;
|
||||
pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
|
||||
pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Check CRT timing values */
|
||||
int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
var->xres = (var->xres+7)&~7;
|
||||
var->left_margin = (var->left_margin+7)&~7;
|
||||
var->right_margin = (var->right_margin+7)&~7;
|
||||
var->hsync_len = (var->hsync_len+7)&~7;
|
||||
|
||||
/* Check horizontal total */
|
||||
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
|
||||
if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check horizontal display and blank start */
|
||||
value = var->xres;
|
||||
if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
|
||||
return -EINVAL;
|
||||
if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check horizontal sync start */
|
||||
value = var->xres + var->right_margin;
|
||||
if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check horizontal blank end (or length) */
|
||||
value = var->left_margin + var->right_margin + var->hsync_len;
|
||||
if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check horizontal sync end (or length) */
|
||||
value = var->hsync_len;
|
||||
if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check vertical total */
|
||||
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
|
||||
if ((value - 1) >= svga_regset_size(tm->v_total_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check vertical display and blank start */
|
||||
value = var->yres;
|
||||
if ((value - 1) >= svga_regset_size(tm->v_display_regs))
|
||||
return -EINVAL;
|
||||
if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check vertical sync start */
|
||||
value = var->yres + var->lower_margin;
|
||||
if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check vertical blank end (or length) */
|
||||
value = var->upper_margin + var->lower_margin + var->vsync_len;
|
||||
if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
|
||||
return -EINVAL;
|
||||
|
||||
/* Check vertical sync end (or length) */
|
||||
value = var->vsync_len;
|
||||
if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set CRT timing registers */
|
||||
void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var,
|
||||
u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
|
||||
{
|
||||
u8 regval;
|
||||
u32 value;
|
||||
|
||||
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal total : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5);
|
||||
|
||||
value = var->xres;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal display : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1);
|
||||
|
||||
value = var->xres;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal blank start: %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder);
|
||||
|
||||
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal blank end : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder);
|
||||
|
||||
value = var->xres + var->right_margin;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal sync start : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_sync_start_regs, (value / 8));
|
||||
|
||||
value = var->xres + var->right_margin + var->hsync_len;
|
||||
value = (value * hmul) / hdiv;
|
||||
pr_debug("fb%d: horizontal sync end : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->h_sync_end_regs, (value / 8));
|
||||
|
||||
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical total : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_total_regs, value - 2);
|
||||
|
||||
value = var->yres;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical display : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_display_regs, value - 1);
|
||||
|
||||
value = var->yres;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical blank start : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_blank_start_regs, value);
|
||||
|
||||
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical blank end : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_blank_end_regs, value - 2);
|
||||
|
||||
value = var->yres + var->lower_margin;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical sync start : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_sync_start_regs, value);
|
||||
|
||||
value = var->yres + var->lower_margin + var->vsync_len;
|
||||
value = (value * vmul) / vdiv;
|
||||
pr_debug("fb%d: vertical sync end : %d\n", node, value);
|
||||
svga_wcrt_multi(tm->v_sync_end_regs, value);
|
||||
|
||||
/* Set horizontal and vertical sync pulse polarity in misc register */
|
||||
|
||||
regval = vga_r(NULL, VGA_MIS_R);
|
||||
if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
|
||||
pr_debug("fb%d: positive horizontal sync\n", node);
|
||||
regval = regval & ~0x80;
|
||||
} else {
|
||||
pr_debug("fb%d: negative horizontal sync\n", node);
|
||||
regval = regval | 0x80;
|
||||
}
|
||||
if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
|
||||
pr_debug("fb%d: positive vertical sync\n", node);
|
||||
regval = regval & ~0x40;
|
||||
} else {
|
||||
pr_debug("fb%d: negative vertical sync\n\n", node);
|
||||
regval = regval | 0x40;
|
||||
}
|
||||
vga_w(NULL, VGA_MIS_W, regval);
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
|
||||
{
|
||||
if ((var->bits_per_pixel == frm->bits_per_pixel) &&
|
||||
(var->red.length <= frm->red.length) &&
|
||||
(var->green.length <= frm->green.length) &&
|
||||
(var->blue.length <= frm->blue.length) &&
|
||||
(var->transp.length <= frm->transp.length) &&
|
||||
(var->nonstd == frm->nonstd)) {
|
||||
var->bits_per_pixel = frm->bits_per_pixel;
|
||||
var->red = frm->red;
|
||||
var->green = frm->green;
|
||||
var->blue = frm->blue;
|
||||
var->transp = frm->transp;
|
||||
var->nonstd = frm->nonstd;
|
||||
if (fix != NULL) {
|
||||
fix->type = frm->type;
|
||||
fix->type_aux = frm->type_aux;
|
||||
fix->visual = frm->visual;
|
||||
fix->xpanstep = frm->xpanstep;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
i++;
|
||||
frm++;
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
EXPORT_SYMBOL(svga_wcrt_multi);
|
||||
EXPORT_SYMBOL(svga_wseq_multi);
|
||||
|
||||
EXPORT_SYMBOL(svga_set_default_gfx_regs);
|
||||
EXPORT_SYMBOL(svga_set_default_atc_regs);
|
||||
EXPORT_SYMBOL(svga_set_default_seq_regs);
|
||||
EXPORT_SYMBOL(svga_set_default_crt_regs);
|
||||
EXPORT_SYMBOL(svga_set_textmode_vga_regs);
|
||||
|
||||
EXPORT_SYMBOL(svga_settile);
|
||||
EXPORT_SYMBOL(svga_tilecopy);
|
||||
EXPORT_SYMBOL(svga_tilefill);
|
||||
EXPORT_SYMBOL(svga_tileblit);
|
||||
EXPORT_SYMBOL(svga_tilecursor);
|
||||
|
||||
EXPORT_SYMBOL(svga_compute_pll);
|
||||
EXPORT_SYMBOL(svga_check_timings);
|
||||
EXPORT_SYMBOL(svga_set_timings);
|
||||
EXPORT_SYMBOL(svga_match_format);
|
||||
|
||||
MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
|
||||
MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -49,6 +49,13 @@
|
|||
#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
|
||||
#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
|
||||
#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
|
||||
#define FB_AUX_TEXT_SVGA_GROUP 8 /* 8-15: SVGA tileblit compatible modes */
|
||||
#define FB_AUX_TEXT_SVGA_MASK 7 /* lower three bits says step */
|
||||
#define FB_AUX_TEXT_SVGA_STEP2 8 /* SVGA text mode: text, attr */
|
||||
#define FB_AUX_TEXT_SVGA_STEP4 9 /* SVGA text mode: text, attr, 2 reserved bytes */
|
||||
#define FB_AUX_TEXT_SVGA_STEP8 10 /* SVGA text mode: text, attr, 6 reserved bytes */
|
||||
#define FB_AUX_TEXT_SVGA_STEP16 11 /* SVGA text mode: text, attr, 14 reserved bytes */
|
||||
#define FB_AUX_TEXT_SVGA_LAST 15 /* reserved up to 15 */
|
||||
|
||||
#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
|
||||
#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
#ifndef _LINUX_SVGA_H
|
||||
#define _LINUX_SVGA_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
/* Terminator for register set */
|
||||
|
||||
#define VGA_REGSET_END_VAL 0xFF
|
||||
#define VGA_REGSET_END {VGA_REGSET_END_VAL, 0, 0}
|
||||
|
||||
struct vga_regset {
|
||||
u8 regnum;
|
||||
u8 lowbit;
|
||||
u8 highbit;
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define SVGA_FORMAT_END_VAL 0xFFFF
|
||||
#define SVGA_FORMAT_END {SVGA_FORMAT_END_VAL, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, 0, 0, 0, 0, 0, 0}
|
||||
|
||||
struct svga_fb_format {
|
||||
/* var part */
|
||||
u32 bits_per_pixel;
|
||||
struct fb_bitfield red;
|
||||
struct fb_bitfield green;
|
||||
struct fb_bitfield blue;
|
||||
struct fb_bitfield transp;
|
||||
u32 nonstd;
|
||||
/* fix part */
|
||||
u32 type;
|
||||
u32 type_aux;
|
||||
u32 visual;
|
||||
u32 xpanstep;
|
||||
u32 xresstep;
|
||||
};
|
||||
|
||||
struct svga_timing_regs {
|
||||
const struct vga_regset *h_total_regs;
|
||||
const struct vga_regset *h_display_regs;
|
||||
const struct vga_regset *h_blank_start_regs;
|
||||
const struct vga_regset *h_blank_end_regs;
|
||||
const struct vga_regset *h_sync_start_regs;
|
||||
const struct vga_regset *h_sync_end_regs;
|
||||
|
||||
const struct vga_regset *v_total_regs;
|
||||
const struct vga_regset *v_display_regs;
|
||||
const struct vga_regset *v_blank_start_regs;
|
||||
const struct vga_regset *v_blank_end_regs;
|
||||
const struct vga_regset *v_sync_start_regs;
|
||||
const struct vga_regset *v_sync_end_regs;
|
||||
};
|
||||
|
||||
struct svga_pll {
|
||||
u16 m_min;
|
||||
u16 m_max;
|
||||
u16 n_min;
|
||||
u16 n_max;
|
||||
u16 r_min;
|
||||
u16 r_max; /* r_max < 32 */
|
||||
u32 f_vco_min;
|
||||
u32 f_vco_max;
|
||||
u32 f_base;
|
||||
};
|
||||
|
||||
|
||||
/* Write a value to the attribute register */
|
||||
|
||||
static inline void svga_wattr(u8 index, u8 data)
|
||||
{
|
||||
inb(0x3DA);
|
||||
outb(index, 0x3C0);
|
||||
outb(data, 0x3C0);
|
||||
}
|
||||
|
||||
/* Write a value to a sequence register with a mask */
|
||||
|
||||
static inline void svga_wseq_mask(u8 index, u8 data, u8 mask)
|
||||
{
|
||||
vga_wseq(NULL, index, (data & mask) | (vga_rseq(NULL, index) & ~mask));
|
||||
}
|
||||
|
||||
/* Write a value to a CRT register with a mask */
|
||||
|
||||
static inline void svga_wcrt_mask(u8 index, u8 data, u8 mask)
|
||||
{
|
||||
vga_wcrt(NULL, index, (data & mask) | (vga_rcrt(NULL, index) & ~mask));
|
||||
}
|
||||
|
||||
static inline int svga_primary_device(struct pci_dev *dev)
|
||||
{
|
||||
u16 flags;
|
||||
pci_read_config_word(dev, PCI_COMMAND, &flags);
|
||||
return (flags & PCI_COMMAND_IO);
|
||||
}
|
||||
|
||||
|
||||
void svga_wcrt_multi(const struct vga_regset *regset, u32 value);
|
||||
void svga_wseq_multi(const struct vga_regset *regset, u32 value);
|
||||
|
||||
void svga_set_default_gfx_regs(void);
|
||||
void svga_set_default_atc_regs(void);
|
||||
void svga_set_default_seq_regs(void);
|
||||
void svga_set_default_crt_regs(void);
|
||||
void svga_set_textmode_vga_regs(void);
|
||||
|
||||
void svga_settile(struct fb_info *info, struct fb_tilemap *map);
|
||||
void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area);
|
||||
void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect);
|
||||
void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit);
|
||||
void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor);
|
||||
|
||||
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node);
|
||||
int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node);
|
||||
void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node);
|
||||
|
||||
int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _LINUX_SVGA_H */
|
||||
|
||||
Loading…
Reference in New Issue