drm/radeon/kms: rename gpu_reset to asic_reset
Patch rename gpu_reset to asic_reset in prevision of having gpu_reset doing more stuff than just basic asic reset. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
225758d8ba
commit
a2d07b7438
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@ -492,7 +492,7 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
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return false;
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}
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int evergreen_gpu_reset(struct radeon_device *rdev)
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int evergreen_asic_reset(struct radeon_device *rdev)
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{
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/* FIXME: implement for evergreen */
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return 0;
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@ -1863,7 +1863,7 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev)
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return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
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}
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int r100_gpu_reset(struct radeon_device *rdev)
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int r100_asic_reset(struct radeon_device *rdev)
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{
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uint32_t status;
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@ -3512,7 +3512,7 @@ int r100_resume(struct radeon_device *rdev)
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/* Resume clock before doing reset */
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r100_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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@ -3581,7 +3581,7 @@ int r100_init(struct radeon_device *rdev)
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return r;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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@ -449,7 +449,7 @@ bool r300_gpu_is_lockup(struct radeon_device *rdev)
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return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
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}
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int r300_gpu_reset(struct radeon_device *rdev)
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int r300_asic_reset(struct radeon_device *rdev)
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{
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uint32_t status;
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@ -1333,7 +1333,7 @@ int r300_resume(struct radeon_device *rdev)
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/* Resume clock before doing reset */
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r300_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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@ -1404,7 +1404,7 @@ int r300_init(struct radeon_device *rdev)
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return r;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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@ -234,7 +234,7 @@ int r420_resume(struct radeon_device *rdev)
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/* Resume clock before doing reset */
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r420_clock_resume(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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@ -315,7 +315,7 @@ int r420_init(struct radeon_device *rdev)
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}
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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@ -209,7 +209,7 @@ int r520_resume(struct radeon_device *rdev)
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/* Resume clock before doing reset */
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rv515_clock_startup(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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@ -246,7 +246,7 @@ int r520_init(struct radeon_device *rdev)
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return -EINVAL;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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if (radeon_asic_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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@ -874,7 +874,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
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return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
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}
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int r600_gpu_reset(struct radeon_device *rdev)
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int r600_asic_reset(struct radeon_device *rdev)
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{
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return r600_gpu_soft_reset(rdev);
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}
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@ -748,7 +748,7 @@ struct radeon_asic {
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int (*suspend)(struct radeon_device *rdev);
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void (*vga_set_state)(struct radeon_device *rdev, bool state);
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bool (*gpu_is_lockup)(struct radeon_device *rdev);
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int (*gpu_reset)(struct radeon_device *rdev);
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int (*asic_reset)(struct radeon_device *rdev);
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void (*gart_tlb_flush)(struct radeon_device *rdev);
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int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
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int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
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@ -1157,7 +1157,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
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#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
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#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
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#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
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#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
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#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
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#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
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#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
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#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
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@ -1290,7 +1290,7 @@ extern void r600_scratch_init(struct radeon_device *rdev);
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extern int r600_blit_init(struct radeon_device *rdev);
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extern void r600_blit_fini(struct radeon_device *rdev);
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extern int r600_init_microcode(struct radeon_device *rdev);
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extern int r600_gpu_reset(struct radeon_device *rdev);
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extern int r600_asic_reset(struct radeon_device *rdev);
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/* r600 irq */
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extern int r600_irq_init(struct radeon_device *rdev);
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extern void r600_irq_fini(struct radeon_device *rdev);
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@ -135,7 +135,7 @@ static struct radeon_asic r100_asic = {
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.resume = &r100_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r100_gpu_is_lockup,
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.gpu_reset = &r100_gpu_reset,
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.asic_reset = &r100_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -174,7 +174,7 @@ static struct radeon_asic r200_asic = {
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.resume = &r100_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r100_gpu_is_lockup,
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.gpu_reset = &r100_gpu_reset,
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.asic_reset = &r100_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -212,7 +212,7 @@ static struct radeon_asic r300_asic = {
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.resume = &r300_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -251,7 +251,7 @@ static struct radeon_asic r300_asic_pcie = {
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.resume = &r300_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -289,7 +289,7 @@ static struct radeon_asic r420_asic = {
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.resume = &r420_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -328,7 +328,7 @@ static struct radeon_asic rs400_asic = {
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.resume = &rs400_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rs400_gart_tlb_flush,
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.gart_set_page = &rs400_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -367,7 +367,7 @@ static struct radeon_asic rs600_asic = {
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.resume = &rs600_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rs600_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -406,7 +406,7 @@ static struct radeon_asic rs690_asic = {
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.resume = &rs690_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &r300_gpu_reset,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rs400_gart_tlb_flush,
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.gart_set_page = &rs400_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -445,7 +445,7 @@ static struct radeon_asic rv515_asic = {
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.resume = &rv515_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &rv515_gpu_reset,
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.asic_reset = &rv515_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -484,7 +484,7 @@ static struct radeon_asic r520_asic = {
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.resume = &r520_resume,
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.gpu_reset = &rv515_gpu_reset,
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.asic_reset = &rv515_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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@ -524,7 +524,7 @@ static struct radeon_asic r600_asic = {
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.cp_commit = &r600_cp_commit,
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.vga_set_state = &r600_vga_set_state,
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.gpu_is_lockup = &r600_gpu_is_lockup,
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.gpu_reset = &r600_gpu_reset,
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.asic_reset = &r600_asic_reset,
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.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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.ring_test = &r600_ring_test,
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@ -561,7 +561,7 @@ static struct radeon_asic rs780_asic = {
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.resume = &r600_resume,
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.cp_commit = &r600_cp_commit,
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.vga_set_state = &r600_vga_set_state,
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.gpu_reset = &r600_gpu_reset,
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.asic_reset = &r600_asic_reset,
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.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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.ring_test = &r600_ring_test,
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@ -597,7 +597,7 @@ static struct radeon_asic rv770_asic = {
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.suspend = &rv770_suspend,
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.resume = &rv770_resume,
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.cp_commit = &r600_cp_commit,
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.gpu_reset = &r600_gpu_reset,
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.asic_reset = &r600_asic_reset,
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.gpu_is_lockup = &r600_gpu_is_lockup,
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.vga_set_state = &r600_vga_set_state,
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.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
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@ -636,7 +636,7 @@ static struct radeon_asic evergreen_asic = {
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.resume = &evergreen_resume,
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.cp_commit = NULL,
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.gpu_is_lockup = &evergreen_gpu_is_lockup,
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.gpu_reset = &evergreen_gpu_reset,
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.asic_reset = &evergreen_asic_reset,
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.vga_set_state = &r600_vga_set_state,
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.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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@ -61,7 +61,7 @@ uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
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void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void r100_vga_set_state(struct radeon_device *rdev, bool state);
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bool r100_gpu_is_lockup(struct radeon_device *rdev);
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int r100_gpu_reset(struct radeon_device *rdev);
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int r100_asic_reset(struct radeon_device *rdev);
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u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
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void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
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int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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@ -145,7 +145,7 @@ extern void r300_fini(struct radeon_device *rdev);
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extern int r300_suspend(struct radeon_device *rdev);
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extern int r300_resume(struct radeon_device *rdev);
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extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
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extern int r300_gpu_reset(struct radeon_device *rdev);
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extern int r300_asic_reset(struct radeon_device *rdev);
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extern void r300_ring_start(struct radeon_device *rdev);
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extern void r300_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence);
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@ -214,7 +214,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev);
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*/
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int rv515_init(struct radeon_device *rdev);
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void rv515_fini(struct radeon_device *rdev);
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int rv515_gpu_reset(struct radeon_device *rdev);
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int rv515_asic_reset(struct radeon_device *rdev);
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uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rv515_ring_start(struct radeon_device *rdev);
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@ -255,7 +255,7 @@ int r600_copy_dma(struct radeon_device *rdev,
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int r600_irq_process(struct radeon_device *rdev);
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int r600_irq_set(struct radeon_device *rdev);
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bool r600_gpu_is_lockup(struct radeon_device *rdev);
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int r600_gpu_reset(struct radeon_device *rdev);
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int r600_asic_reset(struct radeon_device *rdev);
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int r600_set_surface_reg(struct radeon_device *rdev, int reg,
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uint32_t tiling_flags, uint32_t pitch,
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uint32_t offset, uint32_t obj_size);
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@ -288,7 +288,7 @@ void evergreen_fini(struct radeon_device *rdev);
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int evergreen_suspend(struct radeon_device *rdev);
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int evergreen_resume(struct radeon_device *rdev);
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bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
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int evergreen_gpu_reset(struct radeon_device *rdev);
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int evergreen_asic_reset(struct radeon_device *rdev);
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void evergreen_bandwidth_update(struct radeon_device *rdev);
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void evergreen_hpd_init(struct radeon_device *rdev);
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void evergreen_hpd_fini(struct radeon_device *rdev);
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@ -619,7 +619,7 @@ int radeon_device_init(struct radeon_device *rdev,
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/* Acceleration not working on AGP card try again
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* with fallback to PCI or PCIE GART
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||||
*/
|
||||
radeon_gpu_reset(rdev);
|
||||
radeon_asic_reset(rdev);
|
||||
radeon_fini(rdev);
|
||||
radeon_agp_disable(rdev);
|
||||
r = radeon_init(rdev);
|
||||
|
|
|
@ -231,7 +231,7 @@ retry:
|
|||
if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
|
||||
/* good news we believe it's a lockup */
|
||||
dev_warn(rdev->dev, "GPU lockup (last fence id 0x%08X)\n", seq);
|
||||
r = radeon_gpu_reset(rdev);
|
||||
r = radeon_asic_reset(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
/* FIXME: what should we do ? marking everyone
|
||||
|
|
|
@ -432,7 +432,7 @@ int rs400_resume(struct radeon_device *rdev)
|
|||
/* setup MC before calling post tables */
|
||||
rs400_mc_program(rdev);
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
RREG32(R_0007C0_CP_STAT));
|
||||
|
@ -496,7 +496,7 @@ int rs400_init(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev,
|
||||
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
|
|
|
@ -601,7 +601,7 @@ int rs600_resume(struct radeon_device *rdev)
|
|||
/* Resume clock before doing reset */
|
||||
rv515_clock_startup(rdev);
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
RREG32(R_0007C0_CP_STAT));
|
||||
|
@ -664,7 +664,7 @@ int rs600_init(struct radeon_device *rdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev,
|
||||
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
|
|
|
@ -653,7 +653,7 @@ int rs690_resume(struct radeon_device *rdev)
|
|||
/* Resume clock before doing reset */
|
||||
rv515_clock_startup(rdev);
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
RREG32(R_0007C0_CP_STAT));
|
||||
|
@ -717,7 +717,7 @@ int rs690_init(struct radeon_device *rdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev,
|
||||
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
|
|
|
@ -227,7 +227,7 @@ int rv515_ga_reset(struct radeon_device *rdev)
|
|||
return -1;
|
||||
}
|
||||
|
||||
int rv515_gpu_reset(struct radeon_device *rdev)
|
||||
int rv515_asic_reset(struct radeon_device *rdev)
|
||||
{
|
||||
uint32_t status;
|
||||
|
||||
|
@ -334,7 +334,7 @@ static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
|
|||
|
||||
tmp = RREG32(0x2140);
|
||||
seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
|
||||
radeon_gpu_reset(rdev);
|
||||
radeon_asic_reset(rdev);
|
||||
tmp = RREG32(0x425C);
|
||||
seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
|
||||
return 0;
|
||||
|
@ -502,7 +502,7 @@ int rv515_resume(struct radeon_device *rdev)
|
|||
/* Resume clock before doing reset */
|
||||
rv515_clock_startup(rdev);
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
RREG32(R_0007C0_CP_STAT));
|
||||
|
@ -572,7 +572,7 @@ int rv515_init(struct radeon_device *rdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
||||
if (radeon_gpu_reset(rdev)) {
|
||||
if (radeon_asic_reset(rdev)) {
|
||||
dev_warn(rdev->dev,
|
||||
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
||||
RREG32(R_000E40_RBBM_STATUS),
|
||||
|
|
Loading…
Reference in a new issue