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drm/tegra: dc: Perform a complete reset sequence 

In order for the reset to be applied properly, the module clock must be
enabled during the assertion.

Signed-off-by: Thierry Reding <treding@nvidia.com>
hifive-unleashed-5.1
Thierry Reding 2017-08-30 17:41:00 +02:00
parent 39e08affec
commit a2f2f7403e
1 changed files with 16 additions and 2 deletions
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18
drivers/gpu/drm/tegra/dc.c
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@ -1997,8 +1997,22 @@ static int tegra_dc_probe(struct platform_device *pdev)
return PTR_ERR(dc->rst);
}
if (!dc->soc->broken_reset)
reset_control_assert(dc->rst);
/* assert reset and disable clock */
if (!dc->soc->broken_reset) {
err = clk_prepare_enable(dc->clk);
if (err < 0)
return err;
usleep_range(2000, 4000);
err = reset_control_assert(dc->rst);
if (err < 0)
return err;
usleep_range(2000, 4000);
clk_disable_unprepare(dc->clk);
}
if (dc->soc->has_powergate) {
if (dc->pipe == 0)