Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and 'clk-imx6sll' into clk-next
* clk-stratix10: clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 * clk-imx: clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: imx: pllv2: avoid using uninitialized values clk: imx6ull: Add epdc_podf instead of sim_podf clk: imx: imx7d: correct video pll clock tree clk: imx: imx7d: add the Keypad Port module clock clk: imx7d: add CAAM clock clk: imx: imx7d: add the snvs clock clk: imx: imx6sx: update cko mux options * clk-bcm: clk: bcm2835: De-assert/assert PLL reset signal when appropriate * clk-cs2000: clk: cs2000: set pm_ops in hibernate-compatible way * clk-imx6sll: clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy muxhifive-unleashed-5.1
Stephen Boyd
commit
a339bdf64a
|
|
@ -0,0 +1,36 @@
|
|||
* Clock bindings for Freescale i.MX6 SLL
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sll-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
|
||||
for the full list of i.MX6 SLL clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6sll-clock.h>
|
||||
|
||||
clks: clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sll-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
||||
};
|
||||
|
||||
uart1: serial@2020000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
|
||||
<&clks IMX6SLL_CLK_UART1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be
|
||||
"intel,stratix10-clkmgr"
|
||||
|
||||
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
|
||||
|
||||
- #clock-cells : from common clock binding, shall be set to 1.
|
||||
|
||||
Example:
|
||||
clkmgr: clock-controller@ffd10000 {
|
||||
compatible = "intel,stratix10-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -91,6 +91,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
|||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-$(CONFIG_ARCH_SPRD) += sprd/
|
||||
obj-$(CONFIG_ARCH_STI) += st/
|
||||
obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi-ng/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
|
|
|
|||
|
|
@ -602,9 +602,7 @@ static void bcm2835_pll_off(struct clk_hw *hw)
|
|||
const struct bcm2835_pll_data *data = pll->data;
|
||||
|
||||
spin_lock(&cprman->regs_lock);
|
||||
cprman_write(cprman, data->cm_ctrl_reg,
|
||||
cprman_read(cprman, data->cm_ctrl_reg) |
|
||||
CM_PLL_ANARST);
|
||||
cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
|
||||
cprman_write(cprman, data->a2w_ctrl_reg,
|
||||
cprman_read(cprman, data->a2w_ctrl_reg) |
|
||||
A2W_PLL_CTRL_PWRDN);
|
||||
|
|
@ -638,6 +636,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
|
|||
cpu_relax();
|
||||
}
|
||||
|
||||
cprman_write(cprman, data->a2w_ctrl_reg,
|
||||
cprman_read(cprman, data->a2w_ctrl_reg) |
|
||||
A2W_PLL_CTRL_PRST_DISABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -549,7 +549,7 @@ static int cs2000_resume(struct device *dev)
|
|||
}
|
||||
|
||||
static const struct dev_pm_ops cs2000_pm_ops = {
|
||||
.resume_early = cs2000_resume,
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)
|
||||
};
|
||||
|
||||
static struct i2c_driver cs2000_driver = {
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ obj-$(CONFIG_SOC_IMX35) += clk-imx35.o
|
|||
obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
|
||||
obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
|
||||
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
|
||||
obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
|
||||
obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &clk_busy_divider_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
|
|
@ -175,7 +175,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &clk_busy_mux_ops;
|
||||
init.flags = 0;
|
||||
init.flags = CLK_IS_CRITICAL;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,340 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx6sll-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
|
||||
#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
|
||||
#define xPLL_CLR(offset) (offset + 0x8)
|
||||
|
||||
static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
|
||||
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
|
||||
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
|
||||
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
|
||||
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
|
||||
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
|
||||
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
|
||||
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
|
||||
static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
|
||||
static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
|
||||
static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
|
||||
static const char *axi_sels[] = {"periph", "axi_alt_sel", };
|
||||
static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
|
||||
static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
|
||||
static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
|
||||
static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
|
||||
static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
|
||||
static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
|
||||
static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
|
||||
static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",};
|
||||
static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
|
||||
static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
|
||||
static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
|
||||
static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
|
||||
static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
|
||||
static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
|
||||
static const char *ecspi_sels[] = { "pll3_60m", "osc", };
|
||||
static const char *uart_sels[] = { "pll3_80m", "osc", };
|
||||
static const char *perclk_sels[] = { "ipg", "osc", };
|
||||
static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
|
||||
|
||||
static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
|
||||
static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
|
||||
|
||||
static struct clk *clks[IMX6SLL_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static const struct clk_div_table post_div_table[] = {
|
||||
{ .val = 2, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 0, .div = 4, },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct clk_div_table video_div_table[] = {
|
||||
{ .val = 0, .div = 1, },
|
||||
{ .val = 1, .div = 2, },
|
||||
{ .val = 2, .div = 1, },
|
||||
{ .val = 3, .div = 4, },
|
||||
{ }
|
||||
};
|
||||
|
||||
static u32 share_count_audio;
|
||||
static u32 share_count_ssi1;
|
||||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
|
||||
clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
|
||||
clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
|
||||
clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
|
||||
|
||||
/* ipp_di clock is external input */
|
||||
clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
|
||||
clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
/* Do not bypass PLLs initially */
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
|
||||
writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0));
|
||||
|
||||
clks[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
clks[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
||||
clks[IMX6SLL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
|
||||
clks[IMX6SLL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
|
||||
clks[IMX6SLL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
|
||||
clks[IMX6SLL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
|
||||
clks[IMX6SLL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
|
||||
clks[IMX6SLL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
|
||||
clks[IMX6SLL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
|
||||
|
||||
clks[IMX6SLL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX6SLL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
clks[IMX6SLL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
|
||||
clks[IMX6SLL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
|
||||
clks[IMX6SLL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
|
||||
clks[IMX6SLL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
|
||||
clks[IMX6SLL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
|
||||
clks[IMX6SLL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
|
||||
clks[IMX6SLL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
|
||||
|
||||
/*
|
||||
* Bit 20 is the reserved and read-only bit, we do this only for:
|
||||
* - Do nothing for usbphy clk_enable/disable
|
||||
* - Keep refcount when do usbphy clk_enable/disable, in that case,
|
||||
* the clk framework many need to enable/disable usbphy's parent
|
||||
*/
|
||||
clks[IMX6SLL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
|
||||
clks[IMX6SLL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
|
||||
|
||||
/*
|
||||
* usbphy*_gate needs to be on after system boots up, and software
|
||||
* never needs to control it anymore.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clks[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL);
|
||||
}
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clks[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clks[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clks[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clks[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
|
||||
clks[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clks[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clks[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clks[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
|
||||
clks[IMX6SLL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clks[IMX6SLL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
|
||||
/* name parent_name mult div */
|
||||
clks[IMX6SLL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clks[IMX6SLL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clks[IMX6SLL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clks[IMX6SLL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
clks[IMX6SLL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clks[IMX6SLL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
|
||||
clks[IMX6SLL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
|
||||
clks[IMX6SLL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0);
|
||||
clks[IMX6SLL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clks[IMX6SLL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
|
||||
clks[IMX6SLL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
|
||||
clks[IMX6SLL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x30, 7, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
|
||||
clks[IMX6SLL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
|
||||
clks[IMX6SLL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
|
||||
clks[IMX6SLL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
|
||||
clks[IMX6SLL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
|
||||
clks[IMX6SLL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
|
||||
|
||||
clks[IMX6SLL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
clks[IMX6SLL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clks[IMX6SLL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clks[IMX6SLL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clks[IMX6SLL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3);
|
||||
clks[IMX6SLL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
|
||||
clks[IMX6SLL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clks[IMX6SLL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clks[IMX6SLL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clks[IMX6SLL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
|
||||
clks[IMX6SLL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clks[IMX6SLL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clks[IMX6SLL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clks[IMX6SLL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clks[IMX6SLL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clks[IMX6SLL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clks[IMX6SLL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clks[IMX6SLL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x30, 12, 3);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9, 3);
|
||||
clks[IMX6SLL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
|
||||
clks[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
|
||||
clks[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
|
||||
|
||||
clks[IMX6SLL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clks[IMX6SLL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clks[IMX6SLL_CLK_AXI_PODF] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clks[IMX6SLL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
|
||||
|
||||
clks[IMX6SLL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI1_SEL] = imx_clk_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
|
||||
|
||||
/* CCGR0 */
|
||||
clks[IMX6SLL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10);
|
||||
clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
|
||||
clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
|
||||
|
||||
/* CCGR1 */
|
||||
clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
|
||||
clks[IMX6SLL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
|
||||
clks[IMX6SLL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
|
||||
clks[IMX6SLL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
|
||||
clks[IMX6SLL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
|
||||
clks[IMX6SLL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10);
|
||||
clks[IMX6SLL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
|
||||
clks[IMX6SLL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
|
||||
clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
|
||||
clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
|
||||
clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
|
||||
|
||||
/* CCGR2 */
|
||||
clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2);
|
||||
clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
|
||||
clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
|
||||
clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
|
||||
clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
|
||||
clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
|
||||
clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
|
||||
|
||||
/* CCGR3 */
|
||||
clks[IMX6SLL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2);
|
||||
clks[IMX6SLL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2);
|
||||
clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
|
||||
clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_OCRAM] = imx_clk_gate_flags("ocram","ahb", base + 0x74, 28, CLK_IS_CRITICAL);
|
||||
|
||||
/* CCGR4 */
|
||||
clks[IMX6SLL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
|
||||
clks[IMX6SLL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
|
||||
clks[IMX6SLL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
|
||||
clks[IMX6SLL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
||||
|
||||
/* CCGR5 */
|
||||
clks[IMX6SLL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clks[IMX6SLL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
|
||||
clks[IMX6SLL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO] = imx_clk_gate2_shared("extern_audio", "extern_audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SLL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SLL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SLL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SLL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SLL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SLL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24);
|
||||
clks[IMX6SLL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24);
|
||||
|
||||
/* CCGR6 */
|
||||
clks[IMX6SLL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clks[IMX6SLL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clks[IMX6SLL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clks[IMX6SLL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
|
||||
/* mask handshake of mmdc */
|
||||
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + 0x4);
|
||||
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/* Lower the AHB clock rate before changing the clock source. */
|
||||
clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
|
||||
|
||||
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL], clks[IMX6SLL_CLK_PLL3_USB_OTG]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_CLK2]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE], clks[IMX6SLL_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]);
|
||||
|
||||
clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);
|
||||
|
|
@ -63,17 +63,17 @@ static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_d
|
|||
static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
|
||||
static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
|
||||
static const char *cko1_sels[] = {
|
||||
"pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
|
||||
"dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
|
||||
"epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
|
||||
"dummy", "dummy", "dummy", "dummy",
|
||||
"vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",
|
||||
"lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
|
||||
};
|
||||
static const char *cko2_sels[] = {
|
||||
"dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
|
||||
"ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
|
||||
"lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
|
||||
"usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
|
||||
"dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
|
||||
"spdif", "asrc", "dummy",
|
||||
"display_axi", "dummy", "osc", "dummy", "dummy",
|
||||
"usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",
|
||||
"can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",
|
||||
"uart_serial", "spdif", "audio", "dummy",
|
||||
};
|
||||
static const char *cko_sels[] = { "cko1", "cko2", };
|
||||
static const char *lvds_sels[] = {
|
||||
|
|
|
|||
|
|
@ -308,7 +308,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6);
|
||||
clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
|
||||
if (clk_on_imx6ul())
|
||||
clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
|
||||
else if (clk_on_imx6ull())
|
||||
clks[IMX6ULL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
|
||||
clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
|
||||
clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
|
||||
clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
|
||||
|
|
|
|||
|
|
@ -51,20 +51,20 @@ static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
|
|||
|
||||
static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };
|
||||
|
||||
static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
|
||||
"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", };
|
||||
"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };
|
||||
|
||||
static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk",
|
||||
"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", };
|
||||
|
||||
static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
|
|
@ -74,8 +74,8 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
|||
|
||||
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
|
||||
"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
|
||||
"pll_video_main_clk", };
|
||||
"pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *dram_phym_sel[] = { "pll_dram_main_clk",
|
||||
"dram_phym_alt_clk", };
|
||||
|
|
@ -86,7 +86,7 @@ static const char *dram_sel[] = { "pll_dram_main_clk",
|
|||
static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
|
||||
"pll_sys_main_clk", "pll_enet_500m_clk",
|
||||
"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
|
||||
"pll_video_main_clk", };
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
|
||||
"pll_sys_main_clk", "pll_enet_500m_clk",
|
||||
|
|
@ -108,62 +108,62 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
|
|||
|
||||
static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
|
||||
"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", };
|
||||
"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
|
||||
"pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
|
||||
"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
|
||||
"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
|
||||
"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
|
||||
|
||||
static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
|
||||
"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
|
||||
"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
|
||||
|
||||
static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
|
||||
"pll_video_main_clk", "ext_clk_3", };
|
||||
"pll_video_post_div", "ext_clk_3", };
|
||||
|
||||
static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
|
||||
|
||||
static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
|
||||
|
||||
static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
|
||||
|
||||
static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
|
||||
|
||||
static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_25m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"ext_clk_4", };
|
||||
|
||||
static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
|
||||
"ext_clk_4", "pll_video_main_clk", };
|
||||
"ext_clk_4", "pll_video_post_div", };
|
||||
|
||||
static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_25m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"ext_clk_4", };
|
||||
|
||||
static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
|
||||
"ext_clk_4", "pll_video_main_clk", };
|
||||
"ext_clk_4", "pll_video_post_div", };
|
||||
|
||||
static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_125m_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_sys_pfd3_clk", };
|
||||
|
||||
static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
|
|
@ -174,7 +174,7 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
|||
static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
|
||||
"pll_enet_500m_clk", "pll_enet_250m_clk",
|
||||
"pll_video_main_clk", };
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
|
||||
|
|
@ -204,22 +204,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
|
|||
|
||||
static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
|
|
@ -279,27 +279,27 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
|
|||
|
||||
static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
|
|
@ -308,23 +308,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
|||
|
||||
static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk",
|
||||
"pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",
|
||||
"pll_sys_pfd7_clk", };
|
||||
|
||||
static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
|
||||
|
||||
static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
|
||||
|
||||
static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
|
||||
|
||||
static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
|
||||
|
||||
static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
|
|
@ -339,12 +339,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
|||
|
||||
static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
|
||||
|
|
@ -358,13 +358,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
|
|||
|
||||
static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "ckil", };
|
||||
"pll_audio_post_div", "pll_video_post_div", "ckil", };
|
||||
|
||||
static const char *lvds1_sel[] = { "pll_arm_main_clk",
|
||||
"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
|
||||
"pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
|
||||
"pll_dram_main_clk", };
|
||||
|
|
@ -433,23 +433,22 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
|
||||
clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
|
||||
|
||||
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
|
||||
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
|
||||
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
|
||||
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
|
||||
clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
|
||||
|
||||
clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
|
||||
clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
|
||||
clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
|
||||
|
|
@ -795,7 +794,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
|
||||
clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
|
||||
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
|
||||
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
|
||||
clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
|
||||
clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
|
||||
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
|
||||
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
|
||||
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
|
||||
clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
|
||||
|
|
@ -857,9 +858,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
|
||||
clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
|
||||
clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
|
||||
clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
|
||||
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
|
||||
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
|
||||
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
|
||||
clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
|
||||
clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
|
||||
clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
|
||||
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
|
||||
|
||||
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
|
||||
|
|
@ -879,12 +884,23 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
|
||||
|
||||
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
|
||||
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
/* set uart module clock's parent clock source that must be great then 80MHz */
|
||||
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
|
||||
clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
|
||||
clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,8 +182,12 @@ static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
unsigned long *prate)
|
||||
{
|
||||
u32 dp_op, dp_mfd, dp_mfn;
|
||||
int ret;
|
||||
|
||||
ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
|
||||
dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -123,6 +123,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
|||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, unsigned long flags)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
|
||||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift)
|
||||
{
|
||||
|
|
@ -137,6 +144,13 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
|
|||
shift, 0x3, 0, &imx_ccm_lock, NULL);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, unsigned long flags)
|
||||
{
|
||||
return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
|
||||
shift, 0x3, 0, &imx_ccm_lock, NULL);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate2_shared(const char *name,
|
||||
const char *parent, void __iomem *reg, u8 shift,
|
||||
unsigned int *share_count)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-y += clk.o
|
||||
obj-y += clk-gate.o
|
||||
obj-y += clk-pll.o
|
||||
obj-y += clk-periph.o
|
||||
obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
|
||||
obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
|
||||
obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
|
||||
obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
|
||||
obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,125 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include "stratix10-clk.h"
|
||||
#include "clk.h"
|
||||
|
||||
#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
|
||||
#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
|
||||
|
||||
static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
|
||||
u32 div = 1, val;
|
||||
|
||||
if (socfpgaclk->fixed_div) {
|
||||
div = socfpgaclk->fixed_div;
|
||||
} else if (socfpgaclk->div_reg) {
|
||||
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
|
||||
val &= GENMASK(socfpgaclk->width - 1, 0);
|
||||
div = (1 << val);
|
||||
}
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
|
||||
u32 div = 1, val;
|
||||
|
||||
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
|
||||
val &= GENMASK(socfpgaclk->width - 1, 0);
|
||||
div = (1 << val);
|
||||
div = div ? 4 : 1;
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
|
||||
{
|
||||
struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
|
||||
u32 mask;
|
||||
u8 parent = 0;
|
||||
|
||||
if (socfpgaclk->bypass_reg) {
|
||||
mask = (0x1 << socfpgaclk->bypass_shift);
|
||||
parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
|
||||
socfpgaclk->bypass_shift);
|
||||
}
|
||||
return parent;
|
||||
}
|
||||
|
||||
static struct clk_ops gateclk_ops = {
|
||||
.recalc_rate = socfpga_gate_clk_recalc_rate,
|
||||
.get_parent = socfpga_gate_get_parent,
|
||||
};
|
||||
|
||||
static const struct clk_ops dbgclk_ops = {
|
||||
.recalc_rate = socfpga_dbg_clk_recalc_rate,
|
||||
.get_parent = socfpga_gate_get_parent,
|
||||
};
|
||||
|
||||
struct clk *s10_register_gate(const char *name, const char *parent_name,
|
||||
const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *regbase, unsigned long gate_reg,
|
||||
unsigned long gate_idx, unsigned long div_reg,
|
||||
unsigned long div_offset, u8 div_width,
|
||||
unsigned long bypass_reg, u8 bypass_shift,
|
||||
u8 fixed_div)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_gate_clk *socfpga_clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
|
||||
if (!socfpga_clk)
|
||||
return NULL;
|
||||
|
||||
socfpga_clk->hw.reg = regbase + gate_reg;
|
||||
socfpga_clk->hw.bit_idx = gate_idx;
|
||||
|
||||
gateclk_ops.enable = clk_gate_ops.enable;
|
||||
gateclk_ops.disable = clk_gate_ops.disable;
|
||||
|
||||
socfpga_clk->fixed_div = fixed_div;
|
||||
|
||||
if (div_reg)
|
||||
socfpga_clk->div_reg = regbase + div_reg;
|
||||
else
|
||||
socfpga_clk->div_reg = NULL;
|
||||
|
||||
socfpga_clk->width = div_width;
|
||||
socfpga_clk->shift = div_offset;
|
||||
|
||||
if (bypass_reg)
|
||||
socfpga_clk->bypass_reg = regbase + bypass_reg;
|
||||
else
|
||||
socfpga_clk->bypass_reg = NULL;
|
||||
socfpga_clk->bypass_shift = bypass_shift;
|
||||
|
||||
if (streq(name, "cs_pdbg_clk"))
|
||||
init.ops = &dbgclk_ops;
|
||||
else
|
||||
init.ops = &gateclk_ops;
|
||||
|
||||
init.name = name;
|
||||
init.flags = flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.parent_names = parent_names ? parent_names : &parent_name;
|
||||
socfpga_clk->hw.hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &socfpga_clk->hw.hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(socfpga_clk);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include "stratix10-clk.h"
|
||||
#include "clk.h"
|
||||
|
||||
#define CLK_MGR_FREE_SHIFT 16
|
||||
#define CLK_MGR_FREE_MASK 0x7
|
||||
#define SWCTRLBTCLKSEN_SHIFT 8
|
||||
|
||||
#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
|
||||
|
||||
static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
|
||||
unsigned long div = 1;
|
||||
u32 val;
|
||||
|
||||
val = readl(socfpgaclk->hw.reg);
|
||||
val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
|
||||
parent_rate /= val;
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
|
||||
unsigned long div = 1;
|
||||
|
||||
if (socfpgaclk->fixed_div) {
|
||||
div = socfpgaclk->fixed_div;
|
||||
} else {
|
||||
if (!socfpgaclk->bypass_reg)
|
||||
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
|
||||
}
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
|
||||
{
|
||||
struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
|
||||
u32 clk_src, mask;
|
||||
u8 parent;
|
||||
|
||||
if (socfpgaclk->bypass_reg) {
|
||||
mask = (0x1 << socfpgaclk->bypass_shift);
|
||||
parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
|
||||
socfpgaclk->bypass_shift);
|
||||
} else {
|
||||
clk_src = readl(socfpgaclk->hw.reg);
|
||||
parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
|
||||
CLK_MGR_FREE_MASK;
|
||||
}
|
||||
return parent;
|
||||
}
|
||||
|
||||
static const struct clk_ops peri_c_clk_ops = {
|
||||
.recalc_rate = clk_peri_c_clk_recalc_rate,
|
||||
.get_parent = clk_periclk_get_parent,
|
||||
};
|
||||
|
||||
static const struct clk_ops peri_cnt_clk_ops = {
|
||||
.recalc_rate = clk_peri_cnt_clk_recalc_rate,
|
||||
.get_parent = clk_periclk_get_parent,
|
||||
};
|
||||
|
||||
struct clk *s10_register_periph(const char *name, const char *parent_name,
|
||||
const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, unsigned long offset)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_periph_clk *periph_clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!periph_clk))
|
||||
return NULL;
|
||||
|
||||
periph_clk->hw.reg = reg + offset;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &peri_c_clk_ops;
|
||||
init.flags = flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.parent_names = parent_names ? parent_names : &parent_name;
|
||||
|
||||
periph_clk->hw.hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &periph_clk->hw.hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(periph_clk);
|
||||
return NULL;
|
||||
}
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
|
||||
const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *regbase, unsigned long offset,
|
||||
u8 fixed_divider, unsigned long bypass_reg,
|
||||
unsigned long bypass_shift)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_periph_clk *periph_clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!periph_clk))
|
||||
return NULL;
|
||||
|
||||
if (offset)
|
||||
periph_clk->hw.reg = regbase + offset;
|
||||
else
|
||||
periph_clk->hw.reg = NULL;
|
||||
|
||||
if (bypass_reg)
|
||||
periph_clk->bypass_reg = regbase + bypass_reg;
|
||||
else
|
||||
periph_clk->bypass_reg = NULL;
|
||||
periph_clk->bypass_shift = bypass_shift;
|
||||
periph_clk->fixed_div = fixed_divider;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &peri_cnt_clk_ops;
|
||||
init.flags = flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.parent_names = parent_names ? parent_names : &parent_name;
|
||||
|
||||
periph_clk->hw.hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &periph_clk->hw.hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(periph_clk);
|
||||
return NULL;
|
||||
}
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include "stratix10-clk.h"
|
||||
#include "clk.h"
|
||||
|
||||
/* Clock Manager offsets */
|
||||
#define CLK_MGR_PLL_CLK_SRC_SHIFT 16
|
||||
#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
|
||||
|
||||
/* PLL Clock enable bits */
|
||||
#define SOCFPGA_PLL_POWER 0
|
||||
#define SOCFPGA_PLL_RESET_MASK 0x2
|
||||
#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
|
||||
#define SOCFPGA_PLL_REFDIV_SHIFT 8
|
||||
#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
|
||||
#define SOCFPGA_PLL_MDIV_SHIFT 24
|
||||
#define SWCTRLBTCLKSEL_MASK 0x200
|
||||
#define SWCTRLBTCLKSEL_SHIFT 9
|
||||
|
||||
#define SOCFPGA_BOOT_CLK "boot_clk"
|
||||
|
||||
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
|
||||
|
||||
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
unsigned long mdiv;
|
||||
unsigned long refdiv;
|
||||
unsigned long reg;
|
||||
unsigned long long vco_freq;
|
||||
|
||||
/* read VCO1 reg for numerator and denominator */
|
||||
reg = readl(socfpgaclk->hw.reg);
|
||||
refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
|
||||
vco_freq = (unsigned long long)parent_rate / refdiv;
|
||||
|
||||
/* Read mdiv and fdiv from the fdbck register */
|
||||
reg = readl(socfpgaclk->hw.reg + 0x4);
|
||||
mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
|
||||
vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
|
||||
|
||||
return (unsigned long)vco_freq;
|
||||
}
|
||||
|
||||
static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
u32 div = 1;
|
||||
|
||||
div = ((readl(socfpgaclk->hw.reg) &
|
||||
SWCTRLBTCLKSEL_MASK) >>
|
||||
SWCTRLBTCLKSEL_SHIFT);
|
||||
div += 1;
|
||||
return parent_rate /= div;
|
||||
}
|
||||
|
||||
|
||||
static u8 clk_pll_get_parent(struct clk_hw *hwclk)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
u32 pll_src;
|
||||
|
||||
pll_src = readl(socfpgaclk->hw.reg);
|
||||
return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
|
||||
CLK_MGR_PLL_CLK_SRC_MASK;
|
||||
}
|
||||
|
||||
static u8 clk_boot_get_parent(struct clk_hw *hwclk)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
u32 pll_src;
|
||||
|
||||
pll_src = readl(socfpgaclk->hw.reg);
|
||||
return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
|
||||
SWCTRLBTCLKSEL_MASK;
|
||||
}
|
||||
|
||||
static int clk_pll_prepare(struct clk_hw *hwclk)
|
||||
{
|
||||
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
|
||||
u32 reg;
|
||||
|
||||
/* Bring PLL out of reset */
|
||||
reg = readl(socfpgaclk->hw.reg);
|
||||
reg |= SOCFPGA_PLL_RESET_MASK;
|
||||
writel(reg, socfpgaclk->hw.reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops clk_pll_ops = {
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.get_parent = clk_pll_get_parent,
|
||||
.prepare = clk_pll_prepare,
|
||||
};
|
||||
|
||||
static struct clk_ops clk_boot_ops = {
|
||||
.recalc_rate = clk_boot_clk_recalc_rate,
|
||||
.get_parent = clk_boot_get_parent,
|
||||
.prepare = clk_pll_prepare,
|
||||
};
|
||||
|
||||
struct clk *s10_register_pll(const char *name, const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, unsigned long offset)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_pll *pll_clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!pll_clk))
|
||||
return NULL;
|
||||
|
||||
pll_clk->hw.reg = reg + offset;
|
||||
|
||||
if (streq(name, SOCFPGA_BOOT_CLK))
|
||||
init.ops = &clk_boot_ops;
|
||||
else
|
||||
init.ops = &clk_pll_ops;
|
||||
|
||||
init.name = name;
|
||||
init.flags = flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.parent_names = parent_names;
|
||||
pll_clk->hw.hw.init = &init;
|
||||
|
||||
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
|
||||
clk_pll_ops.enable = clk_gate_ops.enable;
|
||||
clk_pll_ops.disable = clk_gate_ops.disable;
|
||||
|
||||
clk = clk_register(NULL, &pll_clk->hw.hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(pll_clk);
|
||||
return NULL;
|
||||
}
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <dt-bindings/clock/stratix10-clock.h>
|
||||
|
||||
#include "stratix10-clk.h"
|
||||
|
||||
static const char * const pll_mux[] = { "osc1", "cb_intosc_hs_div2_clk",
|
||||
"f2s_free_clk",};
|
||||
static const char * const cntr_mux[] = { "main_pll", "periph_pll",
|
||||
"osc1", "cb_intosc_hs_div2_clk",
|
||||
"f2s_free_clk"};
|
||||
static const char * const boot_mux[] = { "osc1", "cb_intosc_hs_div2_clk",};
|
||||
|
||||
static const char * const noc_free_mux[] = {"main_noc_base_clk",
|
||||
"peri_noc_base_clk",
|
||||
"osc1", "cb_intosc_hs_div2_clk",
|
||||
"f2s_free_clk"};
|
||||
|
||||
static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
|
||||
static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
|
||||
static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
|
||||
static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
|
||||
static const char * const sdmmc_free_mux[] = {"peri_sdmmc_clk", "boot_clk"};
|
||||
static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
|
||||
static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
|
||||
static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
|
||||
|
||||
static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
|
||||
static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
|
||||
static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
|
||||
|
||||
/* clocks in AO (always on) controller */
|
||||
static const struct stratix10_pll_clock s10_pll_clks[] = {
|
||||
{ STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
|
||||
0x0},
|
||||
{ STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
|
||||
0, 0x74},
|
||||
{ STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
|
||||
0, 0xe4},
|
||||
};
|
||||
|
||||
static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
|
||||
{ STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
|
||||
{ STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
|
||||
{ STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
|
||||
0xF4},
|
||||
{ STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
|
||||
0xF8},
|
||||
};
|
||||
|
||||
static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
|
||||
{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0x48, 0, 0, 0},
|
||||
{ STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
|
||||
0, 0x4C, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x50, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x54, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x58, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x5C, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x60, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0x64, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x68, 0, 0, 0},
|
||||
{ STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
|
||||
0x6C, 0, 0, 0},
|
||||
{ STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xBC, 0, 0, 0},
|
||||
{ STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xC0, 0, 0, 0},
|
||||
{ STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xC4, 0, 0, 0},
|
||||
{ STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xC8, 0, 0, 0},
|
||||
{ STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xCC, 0, 0, 0},
|
||||
{ STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
|
||||
0xD0, 0, 0, 0},
|
||||
{ STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
|
||||
0, 0xD4, 0, 0, 0},
|
||||
{ STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
|
||||
0xD8, 0, 0, 0},
|
||||
{ STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
|
||||
0, 4, 0, 0},
|
||||
{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
|
||||
0, 0, 0, 0x3C, 1},
|
||||
{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
|
||||
0, 0, 4, 0xB0, 0},
|
||||
{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
|
||||
0, 0, 4, 0xB0, 1},
|
||||
{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
|
||||
ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
|
||||
{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
|
||||
ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
|
||||
{ STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
|
||||
ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
|
||||
{ STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
|
||||
ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
|
||||
{ STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
|
||||
ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
|
||||
};
|
||||
|
||||
static const struct stratix10_gate_clock s10_gate_clks[] = {
|
||||
{ STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
|
||||
0, 0, 0, 0, 0x3C, 0, 0},
|
||||
{ STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
|
||||
0, 0, 0, 0, 0, 0, 4},
|
||||
{ STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
|
||||
0, 0, 0, 0, 0, 0, 2},
|
||||
{ STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30,
|
||||
1, 0x70, 0, 2, 0, 0, 0},
|
||||
{ STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30,
|
||||
2, 0x70, 8, 2, 0, 0, 0},
|
||||
{ STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30,
|
||||
3, 0x70, 16, 2, 0, 0, 0},
|
||||
{ STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30,
|
||||
4, 0x70, 24, 2, 0, 0, 0},
|
||||
{ STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30,
|
||||
4, 0x70, 26, 2, 0, 0, 0},
|
||||
{ STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
|
||||
4, 0x70, 28, 1, 0, 0, 0},
|
||||
{ STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30,
|
||||
5, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
|
||||
6, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
|
||||
0, 0, 0, 0, 0xDC, 26, 0},
|
||||
{ STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
|
||||
1, 0, 0, 0, 0xDC, 27, 0},
|
||||
{ STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
|
||||
2, 0, 0, 0, 0xDC, 28, 0},
|
||||
{ STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4,
|
||||
3, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4,
|
||||
4, 0xE0, 0, 16, 0, 0, 0},
|
||||
{ STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4,
|
||||
5, 0, 0, 0, 0, 0, 4},
|
||||
{ STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4,
|
||||
6, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4,
|
||||
7, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
|
||||
8, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
|
||||
9, 0, 0, 0, 0, 0, 0},
|
||||
{ STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4,
|
||||
10, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk *clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_periph(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names, clks[i].num_parents,
|
||||
clks[i].flags, base, clks[i].offset);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.clks[clks[i].id] = clk;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk *clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].offset,
|
||||
clks[i].fixed_divider,
|
||||
clks[i].bypass_reg,
|
||||
clks[i].bypass_shift);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.clks[clks[i].id] = clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk *clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_gate(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].gate_reg,
|
||||
clks[i].gate_idx, clks[i].div_reg,
|
||||
clks[i].div_offset, clks[i].div_width,
|
||||
clks[i].bypass_reg,
|
||||
clks[i].bypass_shift,
|
||||
clks[i].fixed_div);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.clks[clks[i].id] = clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
|
||||
int nums, struct stratix10_clock_data *data)
|
||||
{
|
||||
struct clk *clk;
|
||||
void __iomem *base = data->base;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_pll(clks[i].name, clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].offset);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
continue;
|
||||
}
|
||||
data->clk_data.clks[clks[i].id] = clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
|
||||
int nr_clks)
|
||||
{
|
||||
struct stratix10_clock_data *clk_data;
|
||||
struct clk **clk_table;
|
||||
void __iomem *base;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
pr_err("%s: failed to map clock registers\n", __func__);
|
||||
goto err;
|
||||
}
|
||||
|
||||
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
goto err;
|
||||
|
||||
clk_data->base = base;
|
||||
clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
goto err_data;
|
||||
|
||||
clk_data->clk_data.clks = clk_table;
|
||||
clk_data->clk_data.clk_num = nr_clks;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
|
||||
return clk_data;
|
||||
|
||||
err_data:
|
||||
kfree(clk_data);
|
||||
err:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int s10_clkmgr_init(struct device_node *np)
|
||||
{
|
||||
struct stratix10_clock_data *clk_data;
|
||||
|
||||
clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
|
||||
|
||||
s10_clk_register_c_perip(s10_main_perip_c_clks,
|
||||
ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
|
||||
|
||||
s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
|
||||
ARRAY_SIZE(s10_main_perip_cnt_clks),
|
||||
clk_data);
|
||||
|
||||
s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
|
||||
clk_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s10_clkmgr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
s10_clkmgr_init(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stratix10_clkmgr_match_table[] = {
|
||||
{ .compatible = "intel,stratix10-clkmgr",
|
||||
.data = s10_clkmgr_init },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver stratix10_clkmgr_driver = {
|
||||
.probe = s10_clkmgr_probe,
|
||||
.driver = {
|
||||
.name = "stratix10-clkmgr",
|
||||
.of_match_table = stratix10_clkmgr_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init s10_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&stratix10_clkmgr_driver);
|
||||
}
|
||||
core_initcall(s10_clk_init);
|
||||
|
|
@ -54,9 +54,11 @@ struct socfpga_gate_clk {
|
|||
char *parent_name;
|
||||
u32 fixed_div;
|
||||
void __iomem *div_reg;
|
||||
void __iomem *bypass_reg;
|
||||
struct regmap *sys_mgr_base_addr;
|
||||
u32 width; /* only valid if div_reg != 0 */
|
||||
u32 shift; /* only valid if div_reg != 0 */
|
||||
u32 bypass_shift; /* only valid if bypass_reg != 0 */
|
||||
u32 clk_phase[2];
|
||||
};
|
||||
|
||||
|
|
@ -65,8 +67,10 @@ struct socfpga_periph_clk {
|
|||
char *parent_name;
|
||||
u32 fixed_div;
|
||||
void __iomem *div_reg;
|
||||
void __iomem *bypass_reg;
|
||||
u32 width; /* only valid if div_reg != 0 */
|
||||
u32 shift; /* only valid if div_reg != 0 */
|
||||
u32 bypass_shift; /* only valid if bypass_reg != 0 */
|
||||
};
|
||||
|
||||
#endif /* SOCFPGA_CLK_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __STRATIX10_CLK_H
|
||||
#define __STRATIX10_CLK_H
|
||||
|
||||
struct stratix10_clock_data {
|
||||
struct clk_onecell_data clk_data;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct stratix10_pll_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
};
|
||||
|
||||
struct stratix10_perip_c_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
const char *const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
};
|
||||
|
||||
struct stratix10_perip_cnt_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
const char *const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 fixed_divider;
|
||||
unsigned long bypass_reg;
|
||||
unsigned long bypass_shift;
|
||||
};
|
||||
|
||||
struct stratix10_gate_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
const char *const *parent_names;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long gate_reg;
|
||||
u8 gate_idx;
|
||||
unsigned long div_reg;
|
||||
u8 div_offset;
|
||||
u8 div_width;
|
||||
unsigned long bypass_reg;
|
||||
u8 bypass_shift;
|
||||
u8 fixed_div;
|
||||
};
|
||||
|
||||
struct clk *s10_register_pll(const char *, const char *const *, u8,
|
||||
unsigned long, void __iomem *, unsigned long);
|
||||
|
||||
struct clk *s10_register_periph(const char *, const char *,
|
||||
const char * const *, u8, unsigned long,
|
||||
void __iomem *, unsigned long);
|
||||
struct clk *s10_register_cnt_periph(const char *, const char *,
|
||||
const char * const *, u8,
|
||||
unsigned long, void __iomem *,
|
||||
unsigned long, u8, unsigned long,
|
||||
unsigned long);
|
||||
struct clk *s10_register_gate(const char *, const char *,
|
||||
const char * const *, u8,
|
||||
unsigned long, void __iomem *,
|
||||
unsigned long, unsigned long,
|
||||
unsigned long, unsigned long, u8,
|
||||
unsigned long, u8, u8);
|
||||
#endif /* __STRATIX10_CLK_H */
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2018 NXP.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX6SLL_H
|
||||
|
||||
#define IMX6SLL_CLK_DUMMY 0
|
||||
#define IMX6SLL_CLK_CKIL 1
|
||||
#define IMX6SLL_CLK_OSC 2
|
||||
#define IMX6SLL_PLL1_BYPASS_SRC 3
|
||||
#define IMX6SLL_PLL2_BYPASS_SRC 4
|
||||
#define IMX6SLL_PLL3_BYPASS_SRC 5
|
||||
#define IMX6SLL_PLL4_BYPASS_SRC 6
|
||||
#define IMX6SLL_PLL5_BYPASS_SRC 7
|
||||
#define IMX6SLL_PLL6_BYPASS_SRC 8
|
||||
#define IMX6SLL_PLL7_BYPASS_SRC 9
|
||||
#define IMX6SLL_CLK_PLL1 10
|
||||
#define IMX6SLL_CLK_PLL2 11
|
||||
#define IMX6SLL_CLK_PLL3 12
|
||||
#define IMX6SLL_CLK_PLL4 13
|
||||
#define IMX6SLL_CLK_PLL5 14
|
||||
#define IMX6SLL_CLK_PLL6 15
|
||||
#define IMX6SLL_CLK_PLL7 16
|
||||
#define IMX6SLL_PLL1_BYPASS 17
|
||||
#define IMX6SLL_PLL2_BYPASS 18
|
||||
#define IMX6SLL_PLL3_BYPASS 19
|
||||
#define IMX6SLL_PLL4_BYPASS 20
|
||||
#define IMX6SLL_PLL5_BYPASS 21
|
||||
#define IMX6SLL_PLL6_BYPASS 22
|
||||
#define IMX6SLL_PLL7_BYPASS 23
|
||||
#define IMX6SLL_CLK_PLL1_SYS 24
|
||||
#define IMX6SLL_CLK_PLL2_BUS 25
|
||||
#define IMX6SLL_CLK_PLL3_USB_OTG 26
|
||||
#define IMX6SLL_CLK_PLL4_AUDIO 27
|
||||
#define IMX6SLL_CLK_PLL5_VIDEO 28
|
||||
#define IMX6SLL_CLK_PLL6_ENET 29
|
||||
#define IMX6SLL_CLK_PLL7_USB_HOST 30
|
||||
#define IMX6SLL_CLK_USBPHY1 31
|
||||
#define IMX6SLL_CLK_USBPHY2 32
|
||||
#define IMX6SLL_CLK_USBPHY1_GATE 33
|
||||
#define IMX6SLL_CLK_USBPHY2_GATE 34
|
||||
#define IMX6SLL_CLK_PLL2_PFD0 35
|
||||
#define IMX6SLL_CLK_PLL2_PFD1 36
|
||||
#define IMX6SLL_CLK_PLL2_PFD2 37
|
||||
#define IMX6SLL_CLK_PLL2_PFD3 38
|
||||
#define IMX6SLL_CLK_PLL3_PFD0 39
|
||||
#define IMX6SLL_CLK_PLL3_PFD1 40
|
||||
#define IMX6SLL_CLK_PLL3_PFD2 41
|
||||
#define IMX6SLL_CLK_PLL3_PFD3 42
|
||||
#define IMX6SLL_CLK_PLL4_POST_DIV 43
|
||||
#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
|
||||
#define IMX6SLL_CLK_PLL5_POST_DIV 45
|
||||
#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
|
||||
#define IMX6SLL_CLK_PLL2_198M 47
|
||||
#define IMX6SLL_CLK_PLL3_120M 48
|
||||
#define IMX6SLL_CLK_PLL3_80M 49
|
||||
#define IMX6SLL_CLK_PLL3_60M 50
|
||||
#define IMX6SLL_CLK_STEP 51
|
||||
#define IMX6SLL_CLK_PLL1_SW 52
|
||||
#define IMX6SLL_CLK_AXI_ALT_SEL 53
|
||||
#define IMX6SLL_CLK_AXI_SEL 54
|
||||
#define IMX6SLL_CLK_PERIPH_PRE 55
|
||||
#define IMX6SLL_CLK_PERIPH2_PRE 56
|
||||
#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
|
||||
#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
|
||||
#define IMX6SLL_CLK_PERCLK_SEL 59
|
||||
#define IMX6SLL_CLK_USDHC1_SEL 60
|
||||
#define IMX6SLL_CLK_USDHC2_SEL 61
|
||||
#define IMX6SLL_CLK_USDHC3_SEL 62
|
||||
#define IMX6SLL_CLK_SSI1_SEL 63
|
||||
#define IMX6SLL_CLK_SSI2_SEL 64
|
||||
#define IMX6SLL_CLK_SSI3_SEL 65
|
||||
#define IMX6SLL_CLK_PXP_SEL 66
|
||||
#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
|
||||
#define IMX6SLL_CLK_LCDIF_SEL 68
|
||||
#define IMX6SLL_CLK_EPDC_PRE_SEL 69
|
||||
#define IMX6SLL_CLK_SPDIF_SEL 70
|
||||
#define IMX6SLL_CLK_ECSPI_SEL 71
|
||||
#define IMX6SLL_CLK_UART_SEL 72
|
||||
#define IMX6SLL_CLK_ARM 73
|
||||
#define IMX6SLL_CLK_PERIPH 74
|
||||
#define IMX6SLL_CLK_PERIPH2 75
|
||||
#define IMX6SLL_CLK_PERIPH2_CLK2 76
|
||||
#define IMX6SLL_CLK_PERIPH_CLK2 77
|
||||
#define IMX6SLL_CLK_MMDC_PODF 78
|
||||
#define IMX6SLL_CLK_AXI_PODF 79
|
||||
#define IMX6SLL_CLK_AHB 80
|
||||
#define IMX6SLL_CLK_IPG 81
|
||||
#define IMX6SLL_CLK_PERCLK 82
|
||||
#define IMX6SLL_CLK_USDHC1_PODF 83
|
||||
#define IMX6SLL_CLK_USDHC2_PODF 84
|
||||
#define IMX6SLL_CLK_USDHC3_PODF 85
|
||||
#define IMX6SLL_CLK_SSI1_PRED 86
|
||||
#define IMX6SLL_CLK_SSI2_PRED 87
|
||||
#define IMX6SLL_CLK_SSI3_PRED 88
|
||||
#define IMX6SLL_CLK_SSI1_PODF 89
|
||||
#define IMX6SLL_CLK_SSI2_PODF 90
|
||||
#define IMX6SLL_CLK_SSI3_PODF 91
|
||||
#define IMX6SLL_CLK_PXP_PODF 92
|
||||
#define IMX6SLL_CLK_LCDIF_PRED 93
|
||||
#define IMX6SLL_CLK_LCDIF_PODF 94
|
||||
#define IMX6SLL_CLK_EPDC_SEL 95
|
||||
#define IMX6SLL_CLK_EPDC_PODF 96
|
||||
#define IMX6SLL_CLK_SPDIF_PRED 97
|
||||
#define IMX6SLL_CLK_SPDIF_PODF 98
|
||||
#define IMX6SLL_CLK_ECSPI_PODF 99
|
||||
#define IMX6SLL_CLK_UART_PODF 100
|
||||
|
||||
/* CCGR 0 */
|
||||
#define IMX6SLL_CLK_AIPSTZ1 101
|
||||
#define IMX6SLL_CLK_AIPSTZ2 102
|
||||
#define IMX6SLL_CLK_DCP 103
|
||||
#define IMX6SLL_CLK_UART2_IPG 104
|
||||
#define IMX6SLL_CLK_UART2_SERIAL 105
|
||||
|
||||
/* CCGR 1 */
|
||||
#define IMX6SLL_CLK_ECSPI1 106
|
||||
#define IMX6SLL_CLK_ECSPI2 107
|
||||
#define IMX6SLL_CLK_ECSPI3 108
|
||||
#define IMX6SLL_CLK_ECSPI4 109
|
||||
#define IMX6SLL_CLK_UART3_IPG 110
|
||||
#define IMX6SLL_CLK_UART3_SERIAL 111
|
||||
#define IMX6SLL_CLK_UART4_IPG 112
|
||||
#define IMX6SLL_CLK_UART4_SERIAL 113
|
||||
#define IMX6SLL_CLK_EPIT1 114
|
||||
#define IMX6SLL_CLK_EPIT2 115
|
||||
#define IMX6SLL_CLK_GPT_BUS 116
|
||||
#define IMX6SLL_CLK_GPT_SERIAL 117
|
||||
|
||||
/* CCGR2 */
|
||||
#define IMX6SLL_CLK_CSI 118
|
||||
#define IMX6SLL_CLK_I2C1 119
|
||||
#define IMX6SLL_CLK_I2C2 120
|
||||
#define IMX6SLL_CLK_I2C3 121
|
||||
#define IMX6SLL_CLK_OCOTP 122
|
||||
#define IMX6SLL_CLK_LCDIF_APB 123
|
||||
#define IMX6SLL_CLK_PXP 124
|
||||
|
||||
/* CCGR3 */
|
||||
#define IMX6SLL_CLK_UART5_IPG 125
|
||||
#define IMX6SLL_CLK_UART5_SERIAL 126
|
||||
#define IMX6SLL_CLK_EPDC_AXI 127
|
||||
#define IMX6SLL_CLK_EPDC_PIX 128
|
||||
#define IMX6SLL_CLK_LCDIF_PIX 129
|
||||
#define IMX6SLL_CLK_WDOG1 130
|
||||
#define IMX6SLL_CLK_MMDC_P0_FAST 131
|
||||
#define IMX6SLL_CLK_MMDC_P0_IPG 132
|
||||
#define IMX6SLL_CLK_OCRAM 133
|
||||
|
||||
/* CCGR4 */
|
||||
#define IMX6SLL_CLK_PWM1 134
|
||||
#define IMX6SLL_CLK_PWM2 135
|
||||
#define IMX6SLL_CLK_PWM3 136
|
||||
#define IMX6SLL_CLK_PWM4 137
|
||||
|
||||
/* CCGR 5 */
|
||||
#define IMX6SLL_CLK_ROM 138
|
||||
#define IMX6SLL_CLK_SDMA 139
|
||||
#define IMX6SLL_CLK_KPP 140
|
||||
#define IMX6SLL_CLK_WDOG2 141
|
||||
#define IMX6SLL_CLK_SPBA 142
|
||||
#define IMX6SLL_CLK_SPDIF 143
|
||||
#define IMX6SLL_CLK_SPDIF_GCLK 144
|
||||
#define IMX6SLL_CLK_SSI1 145
|
||||
#define IMX6SLL_CLK_SSI1_IPG 146
|
||||
#define IMX6SLL_CLK_SSI2 147
|
||||
#define IMX6SLL_CLK_SSI2_IPG 148
|
||||
#define IMX6SLL_CLK_SSI3 149
|
||||
#define IMX6SLL_CLK_SSI3_IPG 150
|
||||
#define IMX6SLL_CLK_UART1_IPG 151
|
||||
#define IMX6SLL_CLK_UART1_SERIAL 152
|
||||
|
||||
/* CCGR 6 */
|
||||
#define IMX6SLL_CLK_USBOH3 153
|
||||
#define IMX6SLL_CLK_USDHC1 154
|
||||
#define IMX6SLL_CLK_USDHC2 155
|
||||
#define IMX6SLL_CLK_USDHC3 156
|
||||
|
||||
#define IMX6SLL_CLK_IPP_DI0 157
|
||||
#define IMX6SLL_CLK_IPP_DI1 158
|
||||
#define IMX6SLL_CLK_LDB_DI0_SEL 159
|
||||
#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
|
||||
#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
|
||||
#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
|
||||
#define IMX6SLL_CLK_LDB_DI0 163
|
||||
#define IMX6SLL_CLK_LDB_DI1_SEL 164
|
||||
#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
|
||||
#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
|
||||
#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
|
||||
#define IMX6SLL_CLK_LDB_DI1 168
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
|
||||
#define IMX6SLL_CLK_EXTERN_AUDIO 172
|
||||
|
||||
#define IMX6SLL_CLK_END 173
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
|
||||
|
|
@ -452,5 +452,8 @@
|
|||
#define IMX7D_OCOTP_CLK 439
|
||||
#define IMX7D_NAND_RAWNAND_CLK 440
|
||||
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
|
||||
#define IMX7D_CLK_END 442
|
||||
#define IMX7D_SNVS_CLK 442
|
||||
#define IMX7D_CAAM_CLK 443
|
||||
#define IMX7D_KPP_ROOT_CLK 444
|
||||
#define IMX7D_CLK_END 445
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2017, Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __STRATIX10_CLOCK_H
|
||||
#define __STRATIX10_CLOCK_H
|
||||
|
||||
/* fixed rate clocks */
|
||||
#define STRATIX10_OSC1 0
|
||||
#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1
|
||||
#define STRATIX10_CB_INTOSC_LS_CLK 2
|
||||
#define STRATIX10_F2S_FREE_CLK 3
|
||||
|
||||
/* fixed factor clocks */
|
||||
#define STRATIX10_L4_SYS_FREE_CLK 4
|
||||
#define STRATIX10_MPU_PERIPH_CLK 5
|
||||
#define STRATIX10_MPU_L2RAM_CLK 6
|
||||
#define STRATIX10_SDMMC_CIU_CLK 7
|
||||
|
||||
/* PLL clocks */
|
||||
#define STRATIX10_MAIN_PLL_CLK 8
|
||||
#define STRATIX10_PERIPH_PLL_CLK 9
|
||||
#define STRATIX10_BOOT_CLK 10
|
||||
|
||||
/* Periph clocks */
|
||||
#define STRATIX10_MAIN_MPU_BASE_CLK 11
|
||||
#define STRATIX10_MAIN_NOC_BASE_CLK 12
|
||||
#define STRATIX10_MAIN_EMACA_CLK 13
|
||||
#define STRATIX10_MAIN_EMACB_CLK 14
|
||||
#define STRATIX10_MAIN_EMAC_PTP_CLK 15
|
||||
#define STRATIX10_MAIN_GPIO_DB_CLK 16
|
||||
#define STRATIX10_MAIN_SDMMC_CLK 17
|
||||
#define STRATIX10_MAIN_S2F_USR0_CLK 18
|
||||
#define STRATIX10_MAIN_S2F_USR1_CLK 19
|
||||
#define STRATIX10_MAIN_PSI_REF_CLK 20
|
||||
|
||||
#define STRATIX10_PERI_MPU_BASE_CLK 21
|
||||
#define STRATIX10_PERI_NOC_BASE_CLK 22
|
||||
#define STRATIX10_PERI_EMACA_CLK 23
|
||||
#define STRATIX10_PERI_EMACB_CLK 24
|
||||
#define STRATIX10_PERI_EMAC_PTP_CLK 25
|
||||
#define STRATIX10_PERI_GPIO_DB_CLK 26
|
||||
#define STRATIX10_PERI_SDMMC_CLK 27
|
||||
#define STRATIX10_PERI_S2F_USR0_CLK 28
|
||||
#define STRATIX10_PERI_S2F_USR1_CLK 29
|
||||
#define STRATIX10_PERI_PSI_REF_CLK 30
|
||||
|
||||
#define STRATIX10_MPU_FREE_CLK 31
|
||||
#define STRATIX10_NOC_FREE_CLK 32
|
||||
#define STRATIX10_S2F_USR0_CLK 33
|
||||
#define STRATIX10_NOC_CLK 34
|
||||
#define STRATIX10_EMAC_A_FREE_CLK 35
|
||||
#define STRATIX10_EMAC_B_FREE_CLK 36
|
||||
#define STRATIX10_EMAC_PTP_FREE_CLK 37
|
||||
#define STRATIX10_GPIO_DB_FREE_CLK 38
|
||||
#define STRATIX10_SDMMC_FREE_CLK 39
|
||||
#define STRATIX10_S2F_USER1_FREE_CLK 40
|
||||
#define STRATIX10_PSI_REF_FREE_CLK 41
|
||||
|
||||
/* Gate clocks */
|
||||
#define STRATIX10_MPU_CLK 42
|
||||
#define STRATIX10_L4_MAIN_CLK 43
|
||||
#define STRATIX10_L4_MP_CLK 44
|
||||
#define STRATIX10_L4_SP_CLK 45
|
||||
#define STRATIX10_CS_AT_CLK 46
|
||||
#define STRATIX10_CS_TRACE_CLK 47
|
||||
#define STRATIX10_CS_PDBG_CLK 48
|
||||
#define STRATIX10_CS_TIMER_CLK 49
|
||||
#define STRATIX10_S2F_USER0_CLK 50
|
||||
#define STRATIX10_S2F_USER1_CLK 51
|
||||
#define STRATIX10_EMAC0_CLK 52
|
||||
#define STRATIX10_EMAC1_CLK 53
|
||||
#define STRATIX10_EMAC2_CLK 54
|
||||
#define STRATIX10_EMAC_PTP_CLK 55
|
||||
#define STRATIX10_GPIO_DB_CLK 56
|
||||
#define STRATIX10_SDMMC_CLK 57
|
||||
#define STRATIX10_PSI_REF_CLK 58
|
||||
#define STRATIX10_USB_CLK 59
|
||||
#define STRATIX10_SPI_M_CLK 60
|
||||
#define STRATIX10_NAND_CLK 61
|
||||
#define STRATIX10_NUM_CLKS 62
|
||||
|
||||
#endif /* __STRATIX10_CLOCK_H */
|
||||
Loading…
Reference in New Issue