OpenRISC: DMA
Simple DMA implementation. Allows for allocation of coherent memory (simply uncached) for DMA operations. Signed-off-by: Jonas Bonn <jonas@southpole.se> Reviewed-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Jonas Bonn
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __ASM_OPENRISC_DMA_MAPPING_H
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#define __ASM_OPENRISC_DMA_MAPPING_H
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/*
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* See Documentation/PCI/PCI-DMA-mapping.txt and
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* Documentation/DMA-API.txt for documentation.
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*
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* This file is written with the intention of eventually moving over
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* to largely using asm-generic/dma-mapping-common.h in its place.
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*/
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#include <linux/dma-debug.h>
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#include <asm-generic/dma-coherent.h>
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#include <linux/kmemcheck.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle);
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dma_addr_t or1k_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs);
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void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs);
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void or1k_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir);
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void or1k_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir);
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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void *memory;
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memory = or1k_dma_alloc_coherent(dev, size, dma_handle, flag);
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debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
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return memory;
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
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or1k_dma_free_coherent(dev, size, cpu_addr, dma_handle);
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}
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static inline dma_addr_t dma_map_single(struct device *dev, void *ptr,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_addr_t addr;
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kmemcheck_mark_initialized(ptr, size);
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BUG_ON(!valid_dma_direction(dir));
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addr = or1k_map_page(dev, virt_to_page(ptr),
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(unsigned long)ptr & ~PAGE_MASK, size,
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dir, NULL);
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debug_dma_map_page(dev, virt_to_page(ptr),
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(unsigned long)ptr & ~PAGE_MASK, size,
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dir, addr, true);
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return addr;
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}
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static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
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size_t size,
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enum dma_data_direction dir)
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{
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BUG_ON(!valid_dma_direction(dir));
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or1k_unmap_page(dev, addr, size, dir, NULL);
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debug_dma_unmap_page(dev, addr, size, dir, true);
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}
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static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
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size_t size,
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enum dma_data_direction dir)
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{
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BUG_ON(!valid_dma_direction(dir));
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or1k_sync_single_for_cpu(dev, addr, size, dir);
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debug_dma_sync_single_for_cpu(dev, addr, size, dir);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t addr, size_t size,
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enum dma_data_direction dir)
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{
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BUG_ON(!valid_dma_direction(dir));
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or1k_sync_single_for_device(dev, addr, size, dir);
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debug_dma_sync_single_for_device(dev, addr, size, dir);
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}
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static inline int dma_supported(struct device *dev, u64 dma_mask)
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{
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/* Support 32 bit DMA mask exclusively */
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return dma_mask == 0xffffffffULL;
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}
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static inline int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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return -EIO;
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*dev->dma_mask = dma_mask;
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return 0;
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}
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#endif /* __ASM_OPENRISC_DMA_MAPPING_H */
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@ -0,0 +1,191 @@
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* DMA mapping callbacks...
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* As alloc_coherent is the only DMA callback being used currently, that's
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* the only thing implemented properly. The rest need looking into...
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dma-debug.h>
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#include <asm/cpuinfo.h>
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#include <asm/spr_defs.h>
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#include <asm/tlbflush.h>
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static int page_set_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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unsigned long cl;
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pte_val(*pte) |= _PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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/* Flush page out of dcache */
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for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo.dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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return 0;
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}
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static int page_clear_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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pte_val(*pte) &= ~_PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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return 0;
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}
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/*
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* Alloc "coherent" memory, which for OpenRISC means simply uncached.
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*
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* This function effectively just calls __get_free_pages, sets the
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* cache-inhibit bit on those pages, and makes sure that the pages are
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* flushed out of the cache before they are used.
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*
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*/
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void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp)
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{
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unsigned long va;
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void *page;
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struct mm_walk walk = {
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.pte_entry = page_set_nocache,
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.mm = &init_mm
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};
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page = alloc_pages_exact(size, gfp);
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if (!page)
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return NULL;
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/* This gives us the real physical address of the first page. */
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*dma_handle = __pa(page);
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va = (unsigned long)page;
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/*
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* We need to iterate through the pages, clearing the dcache for
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* them and setting the cache-inhibit bit.
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*/
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if (walk_page_range(va, va + size, &walk)) {
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free_pages_exact(page, size);
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return NULL;
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}
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return (void *)va;
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}
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void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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unsigned long va = (unsigned long)vaddr;
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struct mm_walk walk = {
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.pte_entry = page_clear_nocache,
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.mm = &init_mm
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};
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/* walk_page_range shouldn't be able to fail here */
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WARN_ON(walk_page_range(va, va + size, &walk));
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free_pages_exact(vaddr, size);
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}
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dma_addr_t or1k_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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unsigned long cl;
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dma_addr_t addr = page_to_phys(page) + offset;
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switch (dir) {
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case DMA_TO_DEVICE:
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/* Flush the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo.dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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break;
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case DMA_FROM_DEVICE:
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/* Invalidate the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo.dcache_block_size)
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mtspr(SPR_DCBIR, cl);
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break;
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default:
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/*
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* NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
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* flush nor invalidate the cache here as the area will need
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* to be manually synced anyway.
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*/
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break;
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}
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return addr;
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}
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void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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/* Nothing special to do here... */
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}
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void or1k_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long cl;
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dma_addr_t addr = dma_handle;
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/* Invalidate the dcache for the requested range */
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for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
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mtspr(SPR_DCBIR, cl);
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}
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void or1k_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long cl;
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dma_addr_t addr = dma_handle;
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/* Flush the dcache for the requested range */
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for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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}
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/* Number of entries preallocated for DMA-API debugging */
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#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
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static int __init dma_init(void)
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{
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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return 0;
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}
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fs_initcall(dma_init);
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