ath5k: Update initvals
* Update initvals to match legacy and Sam's HAL Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -811,6 +811,8 @@
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/*
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* DCU transmit filter table 0 (32 entries)
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* each entry contains a 32bit slice of the
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* 128bit tx filter for each DCU (4 slices per DCU)
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*/
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#define AR5K_DCU_TX_FILTER_0_BASE 0x1038
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#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
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@ -819,7 +821,7 @@
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* DCU transmit filter table 1 (16 entries)
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*/
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#define AR5K_DCU_TX_FILTER_1_BASE 0x103c
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#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64))
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#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
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/*
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* DCU clear transmit filter register
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@ -1447,7 +1449,7 @@
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AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
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/*
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* Last beacon timestamp register
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* Last beacon timestamp register (Read Only)
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*/
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#define AR5K_LAST_TSTP 0x8080
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@ -2219,9 +2221,7 @@
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#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */
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/*
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* PHY PAPD probe register [5111+ (?)]
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* Is this only present in 5212 ?
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* Because it's always 0 in 5211 initialization code
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* PHY PAPD probe register [5111+]
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*/
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#define AR5K_PHY_PAPD_PROBE 0x9930
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#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
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@ -2363,21 +2363,21 @@
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#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
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#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
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#define AR_PHY_TIMING_9 0x9998
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#define AR_PHY_TIMING_10 0x999c
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#define AR_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
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#define AR_PHY_TIMING_10_PILOT_MASK_2_S 0
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#define AR5K_PHY_TIMING_9 0x9998
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#define AR5K_PHY_TIMING_10 0x999c
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#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
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#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
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/*
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* Spur mitigation control
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*/
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#define AR_PHY_TIMING_11 0x99a0 /* Register address */
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#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
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#define AR_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
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#define AR_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
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#define AR_PHY_TIMING_11_SPUR_FREQ_SD_S 20
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#define AR_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
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#define AR_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
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#define AR5K_PHY_TIMING_11 0x99a0 /* Register address */
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#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */
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#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
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#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */
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#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
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#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */
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#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */
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/*
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* Gain tables
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@ -2481,11 +2481,7 @@
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/*
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* PHY PCDAC TX power table
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*/
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#define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180
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#define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280
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#define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \
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AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\
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AR5K_PHY_PCDAC_TXPOWER_BASE_5211)
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#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
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#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
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/*
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@ -2566,3 +2562,9 @@
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#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
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#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
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#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
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/*
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* PHY PDADC Tx power table
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*/
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#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
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#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
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@ -457,15 +457,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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* 5210 only comes with RF5110
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*/
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if (ah->ah_version != AR5K_AR5210) {
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if (ah->ah_radio != AR5K_RF5111 &&
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ah->ah_radio != AR5K_RF5112 &&
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ah->ah_radio != AR5K_RF5413 &&
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ah->ah_radio != AR5K_RF2413 &&
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ah->ah_radio != AR5K_RF2425) {
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ATH5K_ERR(ah->ah_sc,
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"invalid phy radio: %u\n", ah->ah_radio);
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return -EINVAL;
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}
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switch (channel->hw_value & CHANNEL_MODES) {
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case CHANNEL_A:
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@ -510,11 +501,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
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return -EINVAL;
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}
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/* PHY access enable */
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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}
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/* PHY access enable */
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ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
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ret = ath5k_hw_write_initvals(ah, mode, change_channel);
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if (ret)
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return ret;
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