ARM: S5PC100: Use generic DMA PL330 driver
This patch makes Samsung S5PC100 to use DMA PL330 driver on DMADEVICE. The S5PC100 uses DMA generic APIs instead of SAMSUNG specific S3C-PL330 APIs. Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
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dafc954304
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a422bd0f6d
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@ -10,7 +10,7 @@ if ARCH_S5PC100
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config CPU_S5PC100
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config CPU_S5PC100
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bool
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bool
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select S5P_EXT_INT
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select S5P_EXT_INT
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select S3C_PL330_DMA
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select SAMSUNG_DMADEV
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help
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help
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Enable S5PC100 CPU support
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Enable S5PC100 CPU support
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@ -33,6 +33,11 @@ static struct clk s5p_clk_otgphy = {
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.name = "otg_phy",
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.name = "otg_phy",
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};
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};
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static struct clk dummy_apb_pclk = {
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.name = "apb_pclk",
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.id = -1,
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};
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static struct clk *clk_src_mout_href_list[] = {
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static struct clk *clk_src_mout_href_list[] = {
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[0] = &s5p_clk_27m,
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[0] = &s5p_clk_27m,
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[1] = &clk_fin_hpll,
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[1] = &clk_fin_hpll,
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@ -454,13 +459,13 @@ static struct clk init_clocks_off[] = {
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.enable = s5pc100_d1_0_ctrl,
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.enable = s5pc100_d1_0_ctrl,
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.ctrlbit = (1 << 2),
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.ctrlbit = (1 << 2),
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}, {
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}, {
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.name = "pdma",
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.name = "dma",
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.devname = "s3c-pl330.1",
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.devname = "s3c-pl330.1",
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.parent = &clk_div_d1_bus.clk,
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.parent = &clk_div_d1_bus.clk,
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.enable = s5pc100_d1_0_ctrl,
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.enable = s5pc100_d1_0_ctrl,
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.ctrlbit = (1 << 1),
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.ctrlbit = (1 << 1),
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}, {
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}, {
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.name = "pdma",
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.name = "dma",
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.devname = "s3c-pl330.0",
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.devname = "s3c-pl330.0",
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.parent = &clk_div_d1_bus.clk,
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.parent = &clk_div_d1_bus.clk,
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.enable = s5pc100_d1_0_ctrl,
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.enable = s5pc100_d1_0_ctrl,
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@ -1276,5 +1281,7 @@ void __init s5pc100_register_clocks(void)
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c24xx_register_clock(&dummy_apb_pclk);
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s3c_pwmclk_init();
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s3c_pwmclk_init();
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}
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}
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@ -1,4 +1,8 @@
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/*
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/* linux/arch/arm/mach-s5pc100/dma.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright (C) 2010 Samsung Electronics Co. Ltd.
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* Copyright (C) 2010 Samsung Electronics Co. Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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*
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@ -17,150 +21,245 @@
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-mapping.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl330.h>
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#include <asm/irq.h>
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#include <plat/devs.h>
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#include <plat/devs.h>
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#include <plat/irqs.h>
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#include <mach/map.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/irqs.h>
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#include <mach/dma.h>
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#include <plat/s3c-pl330-pdata.h>
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static u64 dma_dmamask = DMA_BIT_MASK(32);
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static u64 dma_dmamask = DMA_BIT_MASK(32);
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static struct resource s5pc100_pdma0_resource[] = {
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struct dma_pl330_peri pdma0_peri[30] = {
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[0] = {
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{
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.start = S5PC100_PA_PDMA0,
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.peri_id = (u8)DMACH_UART0_RX,
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.end = S5PC100_PA_PDMA0 + SZ_4K,
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.rqtype = DEVTOMEM,
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.flags = IORESOURCE_MEM,
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}, {
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},
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.peri_id = (u8)DMACH_UART0_TX,
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[1] = {
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.rqtype = MEMTODEV,
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.start = IRQ_PDMA0,
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}, {
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.end = IRQ_PDMA0,
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.peri_id = (u8)DMACH_UART1_RX,
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.flags = IORESOURCE_IRQ,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = DMACH_IRDA,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0S_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_AC97_MICIN,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_AC97_PCMIN,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_AC97_PCMOUT,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_EXTERNAL,
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}, {
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.peri_id = (u8)DMACH_PWM,
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}, {
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.peri_id = (u8)DMACH_SPDIF,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_HSI_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_HSI_TX,
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.rqtype = MEMTODEV,
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},
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},
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};
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};
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static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
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struct dma_pl330_platdata s5pc100_pdma0_pdata = {
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.peri = {
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.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
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[0] = DMACH_UART0_RX,
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.peri = pdma0_peri,
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[1] = DMACH_UART0_TX,
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[2] = DMACH_UART1_RX,
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[3] = DMACH_UART1_TX,
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[4] = DMACH_UART2_RX,
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[5] = DMACH_UART2_TX,
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[6] = DMACH_UART3_RX,
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[7] = DMACH_UART3_TX,
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[8] = DMACH_IRDA,
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[9] = DMACH_I2S0_RX,
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[10] = DMACH_I2S0_TX,
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[11] = DMACH_I2S0S_TX,
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[12] = DMACH_I2S1_RX,
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[13] = DMACH_I2S1_TX,
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[14] = DMACH_I2S2_RX,
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[15] = DMACH_I2S2_TX,
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[16] = DMACH_SPI0_RX,
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[17] = DMACH_SPI0_TX,
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[18] = DMACH_SPI1_RX,
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[19] = DMACH_SPI1_TX,
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[20] = DMACH_SPI2_RX,
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[21] = DMACH_SPI2_TX,
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[22] = DMACH_AC97_MICIN,
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[23] = DMACH_AC97_PCMIN,
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[24] = DMACH_AC97_PCMOUT,
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[25] = DMACH_EXTERNAL,
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[26] = DMACH_PWM,
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[27] = DMACH_SPDIF,
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[28] = DMACH_HSI_RX,
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[29] = DMACH_HSI_TX,
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[30] = DMACH_MAX,
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[31] = DMACH_MAX,
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},
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};
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};
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static struct platform_device s5pc100_device_pdma0 = {
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struct amba_device s5pc100_device_pdma0 = {
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.name = "s3c-pl330",
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.dev = {
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.id = 0,
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.init_name = "dma-pl330.0",
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.num_resources = ARRAY_SIZE(s5pc100_pdma0_resource),
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.resource = s5pc100_pdma0_resource,
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.dev = {
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.dma_mask = &dma_dmamask,
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.dma_mask = &dma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &s5pc100_pdma0_pdata,
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.platform_data = &s5pc100_pdma0_pdata,
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},
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},
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};
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.res = {
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.start = S5PC100_PA_PDMA0,
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static struct resource s5pc100_pdma1_resource[] = {
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.end = S5PC100_PA_PDMA0 + SZ_4K,
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[0] = {
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.start = S5PC100_PA_PDMA1,
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.end = S5PC100_PA_PDMA1 + SZ_4K,
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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[1] = {
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.irq = {IRQ_PDMA0, NO_IRQ},
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.start = IRQ_PDMA1,
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.periphid = 0x00041330,
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.end = IRQ_PDMA1,
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};
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.flags = IORESOURCE_IRQ,
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struct dma_pl330_peri pdma1_peri[30] = {
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{
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.peri_id = (u8)DMACH_UART0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = DMACH_IRDA,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0S_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ0,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ1,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ2,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ3,
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},
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},
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};
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};
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static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
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struct dma_pl330_platdata s5pc100_pdma1_pdata = {
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.peri = {
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.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
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||||||
[0] = DMACH_UART0_RX,
|
.peri = pdma1_peri,
|
||||||
[1] = DMACH_UART0_TX,
|
|
||||||
[2] = DMACH_UART1_RX,
|
|
||||||
[3] = DMACH_UART1_TX,
|
|
||||||
[4] = DMACH_UART2_RX,
|
|
||||||
[5] = DMACH_UART2_TX,
|
|
||||||
[6] = DMACH_UART3_RX,
|
|
||||||
[7] = DMACH_UART3_TX,
|
|
||||||
[8] = DMACH_IRDA,
|
|
||||||
[9] = DMACH_I2S0_RX,
|
|
||||||
[10] = DMACH_I2S0_TX,
|
|
||||||
[11] = DMACH_I2S0S_TX,
|
|
||||||
[12] = DMACH_I2S1_RX,
|
|
||||||
[13] = DMACH_I2S1_TX,
|
|
||||||
[14] = DMACH_I2S2_RX,
|
|
||||||
[15] = DMACH_I2S2_TX,
|
|
||||||
[16] = DMACH_SPI0_RX,
|
|
||||||
[17] = DMACH_SPI0_TX,
|
|
||||||
[18] = DMACH_SPI1_RX,
|
|
||||||
[19] = DMACH_SPI1_TX,
|
|
||||||
[20] = DMACH_SPI2_RX,
|
|
||||||
[21] = DMACH_SPI2_TX,
|
|
||||||
[22] = DMACH_PCM0_RX,
|
|
||||||
[23] = DMACH_PCM0_TX,
|
|
||||||
[24] = DMACH_PCM1_RX,
|
|
||||||
[25] = DMACH_PCM1_TX,
|
|
||||||
[26] = DMACH_MSM_REQ0,
|
|
||||||
[27] = DMACH_MSM_REQ1,
|
|
||||||
[28] = DMACH_MSM_REQ2,
|
|
||||||
[29] = DMACH_MSM_REQ3,
|
|
||||||
[30] = DMACH_MAX,
|
|
||||||
[31] = DMACH_MAX,
|
|
||||||
},
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct platform_device s5pc100_device_pdma1 = {
|
struct amba_device s5pc100_device_pdma1 = {
|
||||||
.name = "s3c-pl330",
|
.dev = {
|
||||||
.id = 1,
|
.init_name = "dma-pl330.1",
|
||||||
.num_resources = ARRAY_SIZE(s5pc100_pdma1_resource),
|
|
||||||
.resource = s5pc100_pdma1_resource,
|
|
||||||
.dev = {
|
|
||||||
.dma_mask = &dma_dmamask,
|
.dma_mask = &dma_dmamask,
|
||||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
.platform_data = &s5pc100_pdma1_pdata,
|
.platform_data = &s5pc100_pdma1_pdata,
|
||||||
},
|
},
|
||||||
};
|
.res = {
|
||||||
|
.start = S5PC100_PA_PDMA1,
|
||||||
static struct platform_device *s5pc100_dmacs[] __initdata = {
|
.end = S5PC100_PA_PDMA1 + SZ_4K,
|
||||||
&s5pc100_device_pdma0,
|
.flags = IORESOURCE_MEM,
|
||||||
&s5pc100_device_pdma1,
|
},
|
||||||
|
.irq = {IRQ_PDMA1, NO_IRQ},
|
||||||
|
.periphid = 0x00041330,
|
||||||
};
|
};
|
||||||
|
|
||||||
static int __init s5pc100_dma_init(void)
|
static int __init s5pc100_dma_init(void)
|
||||||
{
|
{
|
||||||
platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs));
|
amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -20,7 +20,7 @@
|
||||||
#ifndef __MACH_DMA_H
|
#ifndef __MACH_DMA_H
|
||||||
#define __MACH_DMA_H
|
#define __MACH_DMA_H
|
||||||
|
|
||||||
/* This platform uses the common S3C DMA API driver for PL330 */
|
/* This platform uses the common DMA API driver for PL330 */
|
||||||
#include <plat/dma-pl330.h>
|
#include <plat/dma-pl330.h>
|
||||||
|
|
||||||
#endif /* __MACH_DMA_H */
|
#endif /* __MACH_DMA_H */
|
||||||
|
|
Loading…
Reference in a new issue