Fixes for ti81xx for v4.5 merge window. We have hp t410 already booting
in mainline kernel with it's bootloader configured clocks. However, trying to boot dm814x-evm uncovered all kind of issues with the timer clock. To keep t410 booting, these issues need to be fixed in a specific order and this branch contains both device tree and code changes. To summarize the changes, we had missing ranges for clocks to probe, missing aliase for clocks, wrong registers for divder clocks, and bad address for the control module. All these went unnoticed earlier as things worked without errors by luck and I did not pay much attention to them until I got hold of a dm814x-evm and I noticed it did not boot. As these are fixes for features that never worked, these can wait for v4.5 merge window no problem. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWag8GAAoJEBvUPslcq6VzDmwP/3Zcu9WU4C/vTm3zig273PbV qmGMc5FshVmlInBEDE3FaCbE3EFscH1DfGP/rYV6e2bPZNl/NIhns0GlZdPA35TO TgXqijdoEOTqMHuCVQtkZkqPfCDR6JIGfnJ7Hk87gph/zDETRPBalAZKfqzsk2qg rAXOVCLCfhRqPO0Miav+VUS/7xZ8Qsz6ItnRmAr+dv95Wicq9OQoyG3Yrk3XEcDW PMnjoHCLaX9KdIyckLX9gWJP/qOL2eCHve45YliXxNYsh/h0CVSxqBkqhYydNgrm XqUOeRIja3pBV9ov3Y+jQn/9Y4cbKEkw168YQkMk5WNFbHZrAdV35e7JHpm6Q+un oH+w8UmncjwObYwkr6AmgOCTeuvAU76FtlPyD/Ct6oHk2hJjJ18AUCRgiUcZ5NEN Lx0NGWyZmNbMe7aqLHPEsrz+3SBir53xOFp8fElIvNM1eURP7nhBIX5SpNXjrZk1 gpvlHROcZy2kYi5cjcBRHh4kZlHJuWFReLXj7L00YLAR67VHQeq8rZ212WZhef/o PGCBJonr1Tfhpe4iWRU4Z/Tm9c4DyO+yWQcHk/GjphACFEH37gdkH3Qzq4CFKz/6 bQtKd4ky/0G965S2bFk5tljelU/+ro4jryE0yU3ip/5aSTlPb3LeZtd6+TzvUKg0 96brOPxlxBBh/gQ0ExB6 =Mesm -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.5/81xx-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical Merge "omap fixes for 81xx for v4.5 merge window" from Tony Lindgren: Fixes for ti81xx for v4.5 merge window. We have hp t410 already booting in mainline kernel with it's bootloader configured clocks. However, trying to boot dm814x-evm uncovered all kind of issues with the timer clock. To keep t410 booting, these issues need to be fixed in a specific order and this branch contains both device tree and code changes. To summarize the changes, we had missing ranges for clocks to probe, missing aliase for clocks, wrong registers for divder clocks, and bad address for the control module. All these went unnoticed earlier as things worked without errors by luck and I did not pay much attention to them until I got hold of a dm814x-evm and I noticed it did not boot. As these are fixes for features that never worked, these can wait for v4.5 merge window no problem. * tag 'omap-for-v4.5/81xx-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Remove useless check for legacy booting for dm814x ARM: OMAP2+: Enable GPIO for dm814x ARM: dts: Fix dm814x pinctrl address and mask ARM: dts: Fix dm8148 control modules ranges ARM: OMAP2+: Fix timer entries for dm814x ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting ARM: OMAP2+: Add DPPLS clock manager for dm814x clk: ti: Add few dm814x clock aliases ARM: dts: Fix dm814x entries for pllss and prcm
This commit is contained in:
Arnd Bergmann
commit
a436848cc7
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@ -4,18 +4,41 @@
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* published by the Free Software Foundation.
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*/
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&scm_clocks {
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tclkin_ck: tclkin_ck {
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&pllss_clocks {
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timer1_fck: timer1_fck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <3>;
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reg = <0x2e0>;
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};
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timer2_fck: timer2_fck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <6>;
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reg = <0x2e0>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x02f0>;
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};
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};
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&scm_clocks {
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devosc_ck: devosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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compatible = "ti,mux-clock";
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clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
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ti,bit-shift = <21>;
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reg = <0x0040>;
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};
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/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
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@ -25,6 +48,32 @@
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clock-frequency = <27000000>;
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};
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/* Optional 32768Hz crystal or clock on RTCOSC pins */
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rtcosc_ck: rtcosc_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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/* Optional external clock on TCLKIN pin, set rate in baord dts file */
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tclkin_ck: tclkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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virt_20000000_ck: virt_20000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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mpu_ck: mpu_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -49,12 +98,6 @@
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clock-frequency = <48000000>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -69,7 +112,31 @@
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};
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&pllss_clocks {
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&prcm_clocks {
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osc_src_ck: osc_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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mpu_clksrc_ck: mpu_clksrc_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&devosc_ck>, <&rtcdivider_ck>;
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ti,bit-shift = <0>;
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reg = <0x0040>;
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};
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/* Fixed divider clock 0.0016384 * devosc */
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rtcdivider_ck: rtcdivider_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&devosc_ck>;
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clock-mult = <128>;
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clock-div = <78125>;
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};
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aud_clkin0_ck: aud_clkin0_ck {
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#clock-cells = <0>;
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@ -88,22 +155,4 @@
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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timer1_mux_ck: timer1_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <3>;
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reg = <0x2e0>;
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};
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timer2_mux_ck: timer2_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
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&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
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ti,bit-shift = <6>;
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reg = <0x2e0>;
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};
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};
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@ -58,8 +58,10 @@
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ti,hwmods = "l3_main";
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/*
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* See TRM "Table 1-317. L4LS Instance Summary", just deduct
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* 0x1000 from the 1-317 addresses to get the device address
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* See TRM "Table 1-317. L4LS Instance Summary" for hints.
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* It shows the module target agent registers though, so the
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* actual device is typically 0x1000 before the target agent
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* except in cases where the module is larger than 0x1000.
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*/
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l4ls: l4ls@48000000 {
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compatible = "ti,dm814-l4ls", "simple-bus";
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@ -183,10 +185,10 @@
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control: control@140000 {
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compatible = "ti,dm814-scm", "simple-bus";
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reg = <0x140000 0x16d000>;
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reg = <0x140000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x160000 0x16d000>;
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ranges = <0 0x140000 0x20000>;
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scm_conf: scm_conf@0 {
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compatible = "syscon";
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@ -203,19 +205,30 @@
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};
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};
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/*
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* Note that silicon revision 2.1 and older
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* require input enabled (bit 18 set) for all
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* 3.3V I/Os to avoid cumulative hardware damage.
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* For more info, see errata advisory 2.1.87.
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* We leave bit 18 out of function-mask and rely
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* on the bootloader for it.
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*/
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pincntl: pinmux@800 {
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compatible = "pinctrl-single";
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reg = <0x800 0xc38>;
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reg = <0x800 0x438>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x300ff>;
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pinctrl-single,function-mask = <0x307ff>;
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};
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};
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prcm: prcm@180000 {
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compatible = "ti,dm814-prcm", "simple-bus";
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reg = <0x180000 0x4000>;
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reg = <0x180000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x180000 0x2000>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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@ -226,9 +239,13 @@
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};
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};
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/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
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pllss: pllss@1c5000 {
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compatible = "ti,dm814-pllss", "simple-bus";
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reg = <0x1c5000 0x2000>;
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reg = <0x1c5000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1c5000 0x1000>;
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pllss_clocks: clocks {
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#address-cells = <1>;
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@ -612,8 +612,7 @@ void __init ti814x_init_early(void)
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ti814x_clockdomains_init();
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dm814x_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = dm814x_dt_clk_init;
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omap_clk_soc_init = dm814x_dt_clk_init;
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}
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void __init ti816x_init_early(void)
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@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
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static struct omap_hwmod dm814x_timer1_hwmod = {
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.name = "timer1",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer_sys_ck",
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.main_clk = "timer1_fck",
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.dev_attr = &capability_alwon_dev_attr,
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.class = &dm816x_timer_hwmod_class,
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.flags = HWMOD_NO_IDLEST,
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@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = {
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static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm814x_timer1_hwmod,
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.clk = "timer_sys_ck",
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.clk = "timer1_fck",
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.user = OCP_USER_MPU,
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};
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@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
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static struct omap_hwmod dm814x_timer2_hwmod = {
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.name = "timer2",
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.clkdm_name = "alwon_l3s_clkdm",
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.main_clk = "timer_sys_ck",
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.main_clk = "timer2_fck",
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.dev_attr = &capability_alwon_dev_attr,
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.class = &dm816x_timer_hwmod_class,
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.flags = HWMOD_NO_IDLEST,
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@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
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static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
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.master = &dm81xx_l4_ls_hwmod,
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.slave = &dm814x_timer2_hwmod,
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.clk = "timer_sys_ck",
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.clk = "timer2_fck",
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.user = OCP_USER_MPU,
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};
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@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
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/*
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* REVISIT: Test and enable the following once clocks work:
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* dm81xx_l4_ls__gpio1
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* dm81xx_l4_ls__gpio2
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* dm81xx_l4_ls__mailbox
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* dm81xx_alwon_l3_slow__gpmc
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* dm81xx_default_l3_slow__usbss
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@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
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&dm81xx_l4_ls__wd_timer1,
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&dm81xx_l4_ls__i2c1,
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&dm81xx_l4_ls__i2c2,
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&dm81xx_l4_ls__gpio1,
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&dm81xx_l4_ls__gpio2,
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&dm81xx_l4_ls__elm,
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&dm81xx_l4_ls__mcspi1,
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&dm81xx_alwon_l3_fast__tpcc,
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@ -662,6 +662,11 @@ static struct omap_prcm_init_data am3_prm_data __initdata = {
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.index = TI_CLKM_PRM,
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.init = am33xx_prm_init,
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};
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static struct omap_prcm_init_data dm814_pllss_data __initdata = {
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.index = TI_CLKM_PLLSS,
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.init = am33xx_prm_init,
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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@ -715,6 +720,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst =
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#endif
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#ifdef CONFIG_SOC_TI81XX
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{ .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
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{ .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
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{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
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#endif
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#ifdef CONFIG_ARCH_OMAP2
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@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = {
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DT_CLK(NULL, "devosc_ck", "devosc_ck"),
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DT_CLK(NULL, "mpu_ck", "mpu_ck"),
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DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
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DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
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DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
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DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
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DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
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DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
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DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
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DT_CLK(NULL, "timer1_fck", "timer1_fck"),
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DT_CLK(NULL, "timer2_fck", "timer2_fck"),
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DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
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DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
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{ .node_name = NULL },
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@ -195,6 +195,7 @@ enum {
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TI_CLKM_PRM,
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TI_CLKM_SCRM,
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TI_CLKM_CTRL,
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TI_CLKM_PLLSS,
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CLK_MAX_MEMMAPS
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||||
};
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|
|
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|||
Loading…
Reference in a new issue