drm/i915: move shared_dpll into the pipe config
With the big sed-job prep work done this is now really simple. With the exception that we only assign the right shared dpll id in the ->mode_set callback but also depend upon the old one still being around. Until that mess is fixed up we need to jump through a few hoops to keep the old value save. v2: Kill the funny whitespace spotted by Chris. v3: Move the shared_dpll pipe config fixup into this patch as noticed by Ville. Also unconditionally set the shared_dpll with the current one, since otherwise we won't handle direct pch port -> cpu edp transitions correctly. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -914,10 +914,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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if (crtc->shared_dpll < 0)
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if (crtc->config.shared_dpll < 0)
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return NULL;
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return &dev_priv->shared_dplls[crtc->shared_dpll];
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return &dev_priv->shared_dplls[crtc->config.shared_dpll];
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}
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/* For ILK+ */
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@ -3001,7 +3001,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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sel = TRANSC_DPLLB_SEL;
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break;
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}
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if (intel_crtc->shared_dpll == DPLL_ID_PCH_PLL_B)
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if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
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temp |= sel;
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else
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temp &= ~sel;
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@ -3087,7 +3087,7 @@ static void intel_put_shared_dpll(struct intel_crtc *crtc)
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WARN_ON(pll->active);
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}
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crtc->shared_dpll = DPLL_ID_PRIVATE;
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crtc->config.shared_dpll = DPLL_ID_PRIVATE;
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}
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static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
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@ -3143,7 +3143,7 @@ static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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return NULL;
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found:
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crtc->shared_dpll = i;
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crtc->config.shared_dpll = i;
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DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
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if (pll->active == 0) {
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DRM_DEBUG_DRIVER("setting up pll %d\n", i);
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@ -4106,12 +4106,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
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pipe_config->pipe_bpp == 24;
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}
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static int intel_crtc_compute_config(struct drm_crtc *crtc,
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static int intel_crtc_compute_config(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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if (HAS_PCH_SPLIT(dev)) {
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/* FDI link clock is fixed at 2.7G */
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@ -4142,10 +4141,15 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
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}
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if (IS_HASWELL(dev))
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hsw_compute_ips_config(intel_crtc, pipe_config);
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hsw_compute_ips_config(crtc, pipe_config);
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/* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
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* clock survives for now. */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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pipe_config->shared_dpll = crtc->config.shared_dpll;
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if (pipe_config->has_pch_encoder)
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return ironlake_fdi_compute_config(intel_crtc, pipe_config);
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return ironlake_fdi_compute_config(crtc, pipe_config);
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return 0;
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}
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@ -7910,7 +7914,7 @@ encoder_retry:
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if (!pipe_config->port_clock)
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pipe_config->port_clock = pipe_config->adjusted_mode.clock;
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ret = intel_crtc_compute_config(crtc, pipe_config);
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ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
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if (ret < 0) {
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DRM_DEBUG_KMS("CRTC fixup failed\n");
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goto fail;
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@ -252,6 +252,9 @@ struct intel_crtc_config {
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* haswell. */
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struct dpll dpll;
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/* Selected dpll when shared or DPLL_ID_PRIVATE. */
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enum intel_dpll_id shared_dpll;
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int pipe_bpp;
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struct intel_link_m_n dp_m_n;
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@ -316,8 +319,6 @@ struct intel_crtc {
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struct intel_crtc_config config;
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/* We can share PLLs across outputs if the timings match */
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enum intel_dpll_id shared_dpll;
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uint32_t ddi_pll_sel;
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/* reset counter value when the last flip was submitted */
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