ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
The existing code assumes a 19.2 MHz MCLK as the default hardware configuration. This is valid for CherryTrail but not for Baytrail. Add explicit MCLK configuration to set the 19.2 clock on/off depending on DAPM events. This is a prerequisite step to enable devices with Baytrail and RT5645 such as Asus X205TA Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -24,6 +24,9 @@
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#include <linux/acpi.h>
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#include <linux/acpi.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <asm/cpu_device_id.h>
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#include <asm/platform_sst_audio.h>
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#include <linux/clk.h>
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#include <sound/pcm.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc.h>
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@ -45,6 +48,7 @@ struct cht_mc_private {
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struct snd_soc_jack jack;
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struct snd_soc_jack jack;
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struct cht_acpi_card *acpi_card;
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struct cht_acpi_card *acpi_card;
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char codec_name[16];
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char codec_name[16];
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struct clk *mclk;
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};
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};
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static inline struct snd_soc_dai *cht_get_codec_dai(struct snd_soc_card *card)
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static inline struct snd_soc_dai *cht_get_codec_dai(struct snd_soc_card *card)
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@ -65,6 +69,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
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struct snd_soc_dapm_context *dapm = w->dapm;
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struct snd_soc_dapm_context *dapm = w->dapm;
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struct snd_soc_card *card = dapm->card;
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struct snd_soc_card *card = dapm->card;
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struct snd_soc_dai *codec_dai;
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struct snd_soc_dai *codec_dai;
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struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
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int ret;
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int ret;
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codec_dai = cht_get_codec_dai(card);
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codec_dai = cht_get_codec_dai(card);
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@ -73,19 +78,30 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
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return -EIO;
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return -EIO;
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}
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}
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if (!SND_SOC_DAPM_EVENT_OFF(event))
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if (SND_SOC_DAPM_EVENT_ON(event)) {
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return 0;
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if (ctx->mclk) {
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ret = clk_prepare_enable(ctx->mclk);
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if (ret < 0) {
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dev_err(card->dev,
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"could not configure MCLK state");
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return ret;
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}
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}
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} else {
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/* Set codec sysclk source to its internal clock because codec PLL will
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* be off when idle and MCLK will also be off when codec is
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* runtime suspended. Codec needs clock for jack detection and button
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* press. MCLK is turned off with clock framework or ACPI.
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*/
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ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
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48000 * 512, SND_SOC_CLOCK_IN);
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if (ret < 0) {
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dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
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return ret;
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}
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/* Set codec sysclk source to its internal clock because codec PLL will
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if (ctx->mclk)
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* be off when idle and MCLK will also be off by ACPI when codec is
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clk_disable_unprepare(ctx->mclk);
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* runtime suspended. Codec needs clock for jack detection and button
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* press.
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*/
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ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
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0, SND_SOC_CLOCK_IN);
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if (ret < 0) {
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dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
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return ret;
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}
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}
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return 0;
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return 0;
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@ -97,7 +113,7 @@ static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
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SND_SOC_DAPM_MIC("Int Mic", NULL),
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SND_SOC_DAPM_MIC("Int Mic", NULL),
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SND_SOC_DAPM_SPK("Ext Spk", NULL),
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SND_SOC_DAPM_SPK("Ext Spk", NULL),
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SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
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SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
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platform_clock_control, SND_SOC_DAPM_POST_PMD),
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platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
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};
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};
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static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
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static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
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@ -225,6 +241,26 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
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rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack);
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rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack);
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if (ctx->mclk) {
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/*
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* The firmware might enable the clock at
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* boot (this information may or may not
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* be reflected in the enable clock register).
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* To change the rate we must disable the clock
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* first to cover these cases. Due to common
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* clock framework restrictions that do not allow
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* to disable a clock that has not been enabled,
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* we need to enable the clock first.
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*/
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ret = clk_prepare_enable(ctx->mclk);
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if (!ret)
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clk_disable_unprepare(ctx->mclk);
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ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
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if (ret)
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dev_err(runtime->dev, "unable to set MCLK rate\n");
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}
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return ret;
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return ret;
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}
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}
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@ -349,6 +385,18 @@ static struct cht_acpi_card snd_soc_cards[] = {
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static char cht_rt5640_codec_name[16]; /* i2c-<HID>:00 with HID being 8 chars */
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static char cht_rt5640_codec_name[16]; /* i2c-<HID>:00 with HID being 8 chars */
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static bool is_valleyview(void)
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{
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static const struct x86_cpu_id cpu_ids[] = {
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{ X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
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{}
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};
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if (!x86_match_cpu(cpu_ids))
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return false;
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return true;
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}
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static int snd_cht_mc_probe(struct platform_device *pdev)
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static int snd_cht_mc_probe(struct platform_device *pdev)
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{
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{
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int ret_val = 0;
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int ret_val = 0;
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@ -391,6 +439,16 @@ static int snd_cht_mc_probe(struct platform_device *pdev)
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cht_dailink[dai_index].codec_name = cht_rt5640_codec_name;
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cht_dailink[dai_index].codec_name = cht_rt5640_codec_name;
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}
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}
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if (is_valleyview()) {
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drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
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if (IS_ERR(drv->mclk)) {
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dev_err(&pdev->dev,
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"Failed to get MCLK from pmc_plt_clk_3: %ld\n",
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PTR_ERR(drv->mclk));
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return PTR_ERR(drv->mclk);
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}
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}
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snd_soc_card_set_drvdata(card, drv);
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snd_soc_card_set_drvdata(card, drv);
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ret_val = devm_snd_soc_register_card(&pdev->dev, card);
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ret_val = devm_snd_soc_register_card(&pdev->dev, card);
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if (ret_val) {
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if (ret_val) {
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