ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCF
Model and manage DAC/ADC dividers as components in the Core Clock Framework. This should allow us to do some more complex clock management and power control. Also, some of the on-board chip clocks can be exposed to the outside, and this change will make those clocks easier to consume by other parts of the kernel. Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Annaliese McDermond
Mark Brown
parent
fd2df3aeaf
commit
a51b500620
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@ -289,6 +289,68 @@ static const struct clk_ops aic32x4_codec_clkin_ops = {
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.get_parent = clk_aic32x4_codec_clkin_get_parent,
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};
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static int clk_aic32x4_div_prepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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return regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIVEN, AIC32X4_DIVEN);
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}
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static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIVEN, 0);
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}
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static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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u8 divisor;
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divisor = DIV_ROUND_UP(parent_rate, rate);
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if (divisor > 128)
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return -EINVAL;
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return regmap_update_bits(div->regmap, div->reg,
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AIC32X4_DIV_MASK, divisor);
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}
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static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long divisor;
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divisor = DIV_ROUND_UP(*parent_rate, rate);
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if (divisor > 128)
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return -EINVAL;
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return DIV_ROUND_UP(*parent_rate, divisor);
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}
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static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_aic32x4 *div = to_clk_aic32x4(hw);
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unsigned int val;
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regmap_read(div->regmap, div->reg, &val);
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return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
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}
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static const struct clk_ops aic32x4_div_ops = {
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.prepare = clk_aic32x4_div_prepare,
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.unprepare = clk_aic32x4_div_unprepare,
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.set_rate = clk_aic32x4_div_set_rate,
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.round_rate = clk_aic32x4_div_round_rate,
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.recalc_rate = clk_aic32x4_div_recalc_rate,
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};
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static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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{
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.name = "pll",
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@ -306,6 +368,34 @@ static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
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.ops = &aic32x4_codec_clkin_ops,
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.reg = 0,
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},
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{
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.name = "ndac",
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.parent_names = (const char * []) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NDAC,
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},
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{
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.name = "mdac",
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.parent_names = (const char * []) { "ndac" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MDAC,
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},
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{
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.name = "nadc",
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.parent_names = (const char * []) { "codec_clkin" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_NADC,
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},
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{
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.name = "madc",
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.parent_names = (const char * []) { "nadc" },
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.num_parents = 1,
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.ops = &aic32x4_div_ops,
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.reg = AIC32X4_MADC,
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},
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};
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static struct clk *aic32x4_register_clk(struct device *dev,
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@ -52,11 +52,11 @@ struct aic32x4_rate_divs {
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u32 rate;
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unsigned long pll_rate;
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u16 dosr;
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u8 ndac;
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u8 mdac;
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unsigned long ndac_rate;
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unsigned long mdac_rate;
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u8 aosr;
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u8 nadc;
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u8 madc;
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unsigned long nadc_rate;
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unsigned long madc_rate;
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u8 blck_N;
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u8 r_block;
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u8 p_block;
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@ -309,34 +309,54 @@ static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{ 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
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{ 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
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{ 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
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{ 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
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1024000, 24, 1, 1 },
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{ 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
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512000, 24, 1, 1 },
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{ 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
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512000, 24, 1, 1 },
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/* 11.025k rate */
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{ 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
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{ 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
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{ 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
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1411200, 16, 1, 1 },
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{ 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
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705600, 16, 1, 1 },
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/* 16k rate */
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{ 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
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{ 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
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{ 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
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{ 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
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2048000, 12, 1, 1 },
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{ 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
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1024000, 12, 1, 1 },
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{ 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
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1024000, 12, 1, 1 },
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/* 22.05k rate */
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{ 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
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{ 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
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{ 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
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{ 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
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2822400, 8, 1, 1 },
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{ 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
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1411200, 8, 1, 1 },
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{ 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
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1411200, 8, 1, 1 },
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/* 32k rate */
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{ 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
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{ 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
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{ 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
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2048000, 6, 1, 1 },
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{ 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
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2048000, 6, 1, 1 },
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/* 44.1k rate */
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{ 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
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{ 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
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{ 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
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{ 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
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5644800, 4, 1, 1 },
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{ 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
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2822400, 4, 1, 1 },
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{ 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
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2822400, 4, 1, 1 },
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/* 48k rate */
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{ 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
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{ 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
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{ 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
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{ 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
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6144000, 4, 1, 1 },
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{ 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
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3072000, 4, 1, 1 },
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{ 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
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3072000, 4, 1, 1 },
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/* 96k rate */
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{ 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
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{ 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
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6144000, 1, 1, 9 },
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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@ -719,6 +739,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
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struct clk_bulk_data clocks[] = {
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{ .id = "pll" },
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{ .id = "nadc" },
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{ .id = "madc" },
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{ .id = "ndac" },
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{ .id = "mdac" },
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};
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i = aic32x4_get_divs(parent_rate, sample_rate);
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@ -731,7 +755,11 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
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if (ret)
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return ret;
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clk_set_rate(clocks[0].clk, sample_rate);
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clk_set_rate(clocks[0].clk, aic32x4_divs[i].pll_rate);
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clk_set_rate(clocks[1].clk, aic32x4_divs[i].nadc_rate);
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clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
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clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
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clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
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aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
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@ -740,26 +768,10 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
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AIC32X4_BDIVCLK_MASK,
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AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
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/* NDAC divider value */
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snd_soc_component_update_bits(component, AIC32X4_NDAC,
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AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
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/* MDAC divider value */
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snd_soc_component_update_bits(component, AIC32X4_MDAC,
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AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
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/* DOSR MSB & LSB values */
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snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
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snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
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/* NADC divider value */
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snd_soc_component_update_bits(component, AIC32X4_NADC,
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AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
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/* MADC divider value */
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snd_soc_component_update_bits(component, AIC32X4_MADC,
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AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
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/* AOSR value */
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snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
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@ -771,8 +783,8 @@ static int aic32x4_setup_clocks(struct snd_soc_component *component,
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}
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static int aic32x4_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
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@ -987,7 +999,8 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
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int ret;
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struct clk_bulk_data clocks[] = {
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{ .id = "codec_clkin" },
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{ .id = "codec_clkin" },
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{ .id = "pll" },
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};
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ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
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@ -206,6 +206,10 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
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#define AIC32X4_RMICPGANIN_IN1L_10K 0x10
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#define AIC32X4_RMICPGANIN_CM1R_10K 0x40
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/* Common mask and enable for all of the dividers */
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#define AIC32X4_DIVEN BIT(7)
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#define AIC32X4_DIV_MASK GENMASK(6, 0)
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/* Clock Limits */
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#define AIC32X4_MAX_PLL_CLKIN 20000000
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