[media] v4l: s5p-tv: add drivers for HDMI on Samsung S5P platform
Add drivers for HDMI outputs on Samsung platforms from S5P family. Drivers are using: - v4l2 framework - runtime PM Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>hifive-unleashed-5.1
Tomasz Stanislawski
Mauro Carvalho Chehab
parent
5930ab2ba0
commit
a52074ee7a
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@ -971,6 +971,8 @@ config VIDEO_S5P_MIPI_CSIS
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To compile this driver as a module, choose M here: the
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module will be called s5p-csis.
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source "drivers/media/video/s5p-tv/Kconfig"
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#
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# USB Multimedia device configuration
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#
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@ -172,6 +172,7 @@ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV) += s5p-tv/
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obj-$(CONFIG_ARCH_DAVINCI) += davinci/
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@ -0,0 +1,49 @@
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# drivers/media/video/s5p-tv/Kconfig
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#
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# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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# Tomasz Stanislawski <t.stanislaws@samsung.com>
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#
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# Licensed under GPL
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config VIDEO_SAMSUNG_S5P_TV
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bool "Samsung TV driver for S5P platform (experimental)"
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depends on PLAT_S5P
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depends on EXPERIMENTAL
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default n
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---help---
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Say Y here to enable selecting the TV output devices for
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Samsung S5P platform.
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if VIDEO_SAMSUNG_S5P_TV
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config VIDEO_SAMSUNG_S5P_HDMI
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tristate "Samsung HDMI Driver"
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depends on VIDEO_V4L2
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depends on VIDEO_SAMSUNG_S5P_TV
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select VIDEO_SAMSUNG_S5P_HDMIPHY
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help
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Say Y here if you want support for the HDMI output
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interface in S5P Samsung SoC. The driver can be compiled
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as module. It is an auxiliary driver, that exposes a V4L2
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subdev for use by other drivers. This driver requires
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hdmiphy driver to work correctly.
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config VIDEO_SAMSUNG_S5P_HDMI_DEBUG
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bool "Enable debug for HDMI Driver"
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depends on VIDEO_SAMSUNG_S5P_HDMI
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default n
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help
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Enables debugging for HDMI driver.
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config VIDEO_SAMSUNG_S5P_HDMIPHY
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tristate "Samsung HDMIPHY Driver"
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depends on VIDEO_DEV && VIDEO_V4L2 && I2C
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depends on VIDEO_SAMSUNG_S5P_TV
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help
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Say Y here if you want support for the physical HDMI
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interface in S5P Samsung SoC. The driver can be compiled
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as module. It is an I2C driver, that exposes a V4L2
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subdev for use by other drivers.
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endif # VIDEO_SAMSUNG_S5P_TV
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@ -0,0 +1,13 @@
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# drivers/media/video/samsung/tvout/Makefile
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#
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# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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# Tomasz Stanislawski <t.stanislaws@samsung.com>
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#
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# Licensed under GPL
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMIPHY) += s5p-hdmiphy.o
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s5p-hdmiphy-y += hdmiphy_drv.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMI) += s5p-hdmi.o
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s5p-hdmi-y += hdmi_drv.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,188 @@
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/*
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* Samsung HDMI Physical interface driver
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*
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* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
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* Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <media/v4l2-subdev.h>
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MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
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MODULE_DESCRIPTION("Samsung HDMI Physical interface driver");
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MODULE_LICENSE("GPL");
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struct hdmiphy_conf {
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u32 preset;
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const u8 *data;
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};
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static const u8 hdmiphy_conf27[32] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
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0x6B, 0x10, 0x02, 0x51, 0xDf, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xe3, 0x26, 0x00, 0x00, 0x00, 0x00,
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};
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static const u8 hdmiphy_conf74_175[32] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
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0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
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};
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static const u8 hdmiphy_conf74_25[32] = {
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0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
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0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xe0,
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0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
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};
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static const u8 hdmiphy_conf148_5[32] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
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0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
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};
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static const struct hdmiphy_conf hdmiphy_conf[] = {
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{ V4L2_DV_480P59_94, hdmiphy_conf27 },
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{ V4L2_DV_1080P30, hdmiphy_conf74_175 },
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{ V4L2_DV_720P59_94, hdmiphy_conf74_175 },
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{ V4L2_DV_720P60, hdmiphy_conf74_25 },
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{ V4L2_DV_1080P50, hdmiphy_conf148_5 },
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{ V4L2_DV_1080P60, hdmiphy_conf148_5 },
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};
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const u8 *hdmiphy_preset2conf(u32 preset)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(hdmiphy_conf); ++i)
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if (hdmiphy_conf[i].preset == preset)
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return hdmiphy_conf[i].data;
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return NULL;
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}
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static int hdmiphy_s_power(struct v4l2_subdev *sd, int on)
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{
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/* to be implemented */
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return 0;
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}
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static int hdmiphy_s_dv_preset(struct v4l2_subdev *sd,
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struct v4l2_dv_preset *preset)
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{
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const u8 *data;
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u8 buffer[32];
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int ret;
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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struct device *dev = &client->dev;
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dev_info(dev, "s_dv_preset(preset = %d)\n", preset->preset);
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data = hdmiphy_preset2conf(preset->preset);
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if (!data) {
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dev_err(dev, "format not supported\n");
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return -EINVAL;
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}
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/* storing configuration to the device */
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memcpy(buffer, data, 32);
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ret = i2c_master_send(client, buffer, 32);
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if (ret != 32) {
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dev_err(dev, "failed to configure HDMIPHY via I2C\n");
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return -EIO;
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}
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return 0;
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}
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static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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struct device *dev = &client->dev;
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u8 buffer[2];
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int ret;
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dev_info(dev, "s_stream(%d)\n", enable);
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/* going to/from configuration from/to operation mode */
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buffer[0] = 0x1f;
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buffer[1] = enable ? 0x80 : 0x00;
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ret = i2c_master_send(client, buffer, 2);
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if (ret != 2) {
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dev_err(dev, "stream (%d) failed\n", enable);
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return -EIO;
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}
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return 0;
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}
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static const struct v4l2_subdev_core_ops hdmiphy_core_ops = {
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.s_power = hdmiphy_s_power,
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};
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static const struct v4l2_subdev_video_ops hdmiphy_video_ops = {
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.s_dv_preset = hdmiphy_s_dv_preset,
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.s_stream = hdmiphy_s_stream,
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};
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static const struct v4l2_subdev_ops hdmiphy_ops = {
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.core = &hdmiphy_core_ops,
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.video = &hdmiphy_video_ops,
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};
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static int __devinit hdmiphy_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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static struct v4l2_subdev sd;
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v4l2_i2c_subdev_init(&sd, client, &hdmiphy_ops);
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dev_info(&client->dev, "probe successful\n");
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return 0;
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}
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static int __devexit hdmiphy_remove(struct i2c_client *client)
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{
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dev_info(&client->dev, "remove successful\n");
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return 0;
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}
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static const struct i2c_device_id hdmiphy_id[] = {
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{ "hdmiphy", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(i2c, hdmiphy_id);
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static struct i2c_driver hdmiphy_driver = {
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.driver = {
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.name = "s5p-hdmiphy",
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.owner = THIS_MODULE,
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},
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.probe = hdmiphy_probe,
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.remove = __devexit_p(hdmiphy_remove),
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.id_table = hdmiphy_id,
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};
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static int __init hdmiphy_init(void)
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{
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return i2c_add_driver(&hdmiphy_driver);
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}
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module_init(hdmiphy_init);
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static void __exit hdmiphy_exit(void)
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{
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i2c_del_driver(&hdmiphy_driver);
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}
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module_exit(hdmiphy_exit);
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@ -0,0 +1,141 @@
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/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* HDMI register header file for Samsung TVOUT driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef SAMSUNG_REGS_HDMI_H
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#define SAMSUNG_REGS_HDMI_H
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/*
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* Register part
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*/
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#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
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#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
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#define HDMI_TG_BASE(x) ((x) + 0x00050000)
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/* Control registers */
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#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
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#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
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#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
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#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
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#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018)
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#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C)
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#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
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/* Core registers */
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#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
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#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
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#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
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#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
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#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014)
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#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
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#define HDMI_HPD HDMI_CORE_BASE(0x0030)
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#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
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#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
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#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
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#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
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#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
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#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
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#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
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#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
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#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
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#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
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#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
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#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
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#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
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#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
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#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
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#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
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#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
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#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
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#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
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#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
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#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
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#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
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#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
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#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
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#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
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#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
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#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
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#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
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#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
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#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300)
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#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
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#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0)
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#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
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#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)
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/* Timing generator registers */
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#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
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#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
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#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
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#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
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#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
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#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
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#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
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#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
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#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
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#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
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#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
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#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
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#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
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#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
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#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
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#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
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#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
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#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
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#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
|
||||
#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
|
||||
#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
|
||||
#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
|
||||
#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
|
||||
#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
|
||||
#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
|
||||
#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
|
||||
#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
|
||||
#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
|
||||
#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
|
||||
|
||||
/*
|
||||
* Bit definition part
|
||||
*/
|
||||
|
||||
/* HDMI_INTC_CON */
|
||||
#define HDMI_INTC_EN_GLOBAL (1 << 6)
|
||||
#define HDMI_INTC_EN_HPD_PLUG (1 << 3)
|
||||
#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
|
||||
|
||||
/* HDMI_INTC_FLAG */
|
||||
#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
|
||||
#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
|
||||
|
||||
/* HDMI_PHY_RSTOUT */
|
||||
#define HDMI_PHY_SW_RSTOUT (1 << 0)
|
||||
|
||||
/* HDMI_CORE_RSTOUT */
|
||||
#define HDMI_CORE_SW_RSTOUT (1 << 0)
|
||||
|
||||
/* HDMI_CON_0 */
|
||||
#define HDMI_BLUE_SCR_EN (1 << 5)
|
||||
#define HDMI_EN (1 << 0)
|
||||
|
||||
/* HDMI_PHY_STATUS */
|
||||
#define HDMI_PHY_STATUS_READY (1 << 0)
|
||||
|
||||
/* HDMI_MODE_SEL */
|
||||
#define HDMI_MODE_HDMI_EN (1 << 1)
|
||||
#define HDMI_MODE_DVI_EN (1 << 0)
|
||||
#define HDMI_MODE_MASK (3 << 0)
|
||||
|
||||
/* HDMI_TG_CMD */
|
||||
#define HDMI_TG_EN (1 << 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_HDMI_H */
|
||||
Loading…
Reference in New Issue