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ARM64: dts: imx8mq: add csi and mipi csi node 

add csi bridge and mipi csi node

Signed-off-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 7028095660d45064d7a1404c26b9a4f00d034043)
5.4-rM2-2.2.x-imx-squashed
Robby Cai 2019-09-30 19:11:18 +08:00 committed by Dong Aisheng
parent 0aea80b560
commit a532ea7777
1 changed files with 60 additions and 0 deletions
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60
arch/arm64/boot/dts/freescale/imx8mq.dtsi
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@ -20,6 +20,8 @@
#size-cells = <2>;
aliases {
csi0 = &mipi_csi_1;
csi1 = &mipi_csi_2;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@ -1043,6 +1045,35 @@
status = "disabled";
};
mipi_csi_1: mipi_csi1@30a70000 {
compatible = "fsl,mxc-mipi-csi2_yav";
reg = <0x30a70000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_ESC>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>;
clock-names = "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
<&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
power-domains = <&pgc_mipi_csi1>;
csis-phy-reset = <&src 0x4c 7>;
phy-gpr = <&iomuxc_gpr 0x88>;
status = "disabled";
};
csi1_bridge: csi1_bridge@30a90000 {
compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
reg = <0x30a90000 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_CSI1_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
mu: mu@30aa0000 {
compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
@ -1084,6 +1115,35 @@
status = "disabled";
};
mipi_csi_2: mipi_csi2@30b60000 {
compatible = "fsl,mxc-mipi-csi2_yav";
reg = <0x30b60000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_ESC>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>;
clock-names = "clk_core", "clk_esc", "clk_pxl";
assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>,
<&clk IMX8MQ_CLK_CSI2_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
power-domains = <&pgc_mipi_csi2>;
csis-phy-reset = <&src 0x50 7>;
phy-gpr = <&iomuxc_gpr 0xa4>;
status = "disabled";
};
csi2_bridge: csi2_bridge@30b80000 {
compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
reg = <0x30b80000 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_CSI2_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
qspi0: spi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;