redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

drm/i915/icl: Refactor icl pll functions

Browse source 
This patch adds helper function for identifying
whether the given PLL is combo PHY PLL or not.
This helper function is used inside various ICL
functions to make them scalable.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-6-mahesh1.kumar@intel.com
This commit is contained in:
Vandita Kulkarni 2018-10-03 12:52:00 +05:30 committed by Rodrigo Vivi
parent 8ea59e6739
commit a54270d3a9
3 changed files with 19 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/i915/intel_display.c
View file

@ -9274,7 +9274,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1)) if (WARN_ON(!intel_dpll_is_combophy(id)))
return; return;
} else if (intel_port_is_tc(dev_priv, port)) { } else if (intel_port_is_tc(dev_priv, port)) {
id = icl_port_to_mg_pll_id(port); id = icl_port_to_mg_pll_id(port);

54
drivers/gpu/drm/i915/intel_dpll_mgr.c
View file

@ -2626,6 +2626,11 @@ enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
return port - PORT_C + DPLL_ID_ICL_MGPLL1; return port - PORT_C + DPLL_ID_ICL_MGPLL1;
} }
bool intel_dpll_is_combophy(enum intel_dpll_id id)
{
return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
}
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
uint32_t *target_dco_khz, uint32_t *target_dco_khz,
struct intel_dpll_hw_state *state) struct intel_dpll_hw_state *state)
@ -2919,22 +2924,17 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id) static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
{ {
switch (id) { if (intel_dpll_is_combophy(id))
default:
MISSING_CASE(id);
/* fall through */
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
return CNL_DPLL_ENABLE(id); return CNL_DPLL_ENABLE(id);
case DPLL_ID_ICL_TBTPLL: else if (id == DPLL_ID_ICL_TBTPLL)
return TBT_PLL_ENABLE; return TBT_PLL_ENABLE;
case DPLL_ID_ICL_MGPLL1: else
case DPLL_ID_ICL_MGPLL2: /*
case DPLL_ID_ICL_MGPLL3: * TODO: Make MG_PLL macros use
case DPLL_ID_ICL_MGPLL4: * tc port id instead of port id
*/
return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id)); return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
} }
}
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll, struct intel_shared_dpll *pll,
@ -2952,17 +2952,11 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE)) if (!(val & PLL_ENABLE))
goto out; goto out;
switch (id) { if (intel_dpll_is_combophy(id) ||
case DPLL_ID_ICL_DPLL0: id == DPLL_ID_ICL_TBTPLL) {
case DPLL_ID_ICL_DPLL1:
case DPLL_ID_ICL_TBTPLL:
hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id)); hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id)); hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
break; } else {
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
case DPLL_ID_ICL_MGPLL4:
port = icl_mg_pll_id_to_port(id); port = icl_mg_pll_id_to_port(id);
hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port)); hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
@ -3000,9 +2994,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
break;
default:
MISSING_CASE(id);
} }
ret = true; ret = true;
@ -3091,21 +3082,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
PLL_POWER_STATE, 1)) PLL_POWER_STATE, 1))
DRM_ERROR("PLL %d Power not enabled\n", id); DRM_ERROR("PLL %d Power not enabled\n", id);
switch (id) { if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
case DPLL_ID_ICL_DPLL0:
case DPLL_ID_ICL_DPLL1:
case DPLL_ID_ICL_TBTPLL:
icl_dpll_write(dev_priv, pll); icl_dpll_write(dev_priv, pll);
break; else
case DPLL_ID_ICL_MGPLL1:
case DPLL_ID_ICL_MGPLL2:
case DPLL_ID_ICL_MGPLL3:
case DPLL_ID_ICL_MGPLL4:
icl_mg_pll_write(dev_priv, pll); icl_mg_pll_write(dev_priv, pll);
break;
default:
MISSING_CASE(id);
}
/* /*
* DVFS pre sequence would be here, but in our driver the cdclk code * DVFS pre sequence would be here, but in our driver the cdclk code

1
drivers/gpu/drm/i915/intel_dpll_mgr.h
View file

@ -346,5 +346,6 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
uint32_t pll_id); uint32_t pll_id);
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
enum intel_dpll_id icl_port_to_mg_pll_id(enum port port); enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
#endif /* _INTEL_DPLL_MGR_H_ */ #endif /* _INTEL_DPLL_MGR_H_ */