V4L/DVB (7669): pxa_camera: Add support for YUV modes
This patch adds support for YUV packed and planar capture for pxa_camera. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>hifive-unleashed-5.1
parent
587df9fca6
commit
a5462e5be3
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@ -49,6 +49,9 @@
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#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
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#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
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#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
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#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
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#define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
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#define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
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#define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
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#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
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#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
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#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
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#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
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@ -70,6 +73,19 @@ static DEFINE_MUTEX(camera_lock);
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/*
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/*
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* Structures
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* Structures
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*/
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*/
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enum pxa_camera_active_dma {
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DMA_Y = 0x1,
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DMA_U = 0x2,
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DMA_V = 0x4,
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};
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/* descriptor needed for the PXA DMA engine */
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struct pxa_cam_dma {
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dma_addr_t sg_dma;
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struct pxa_dma_desc *sg_cpu;
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size_t sg_size;
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int sglen;
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};
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/* buffer for one video frame */
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/* buffer for one video frame */
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struct pxa_buffer {
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struct pxa_buffer {
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@ -78,11 +94,12 @@ struct pxa_buffer {
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const struct soc_camera_data_format *fmt;
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const struct soc_camera_data_format *fmt;
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/* our descriptor list needed for the PXA DMA engine */
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/* our descriptor lists for Y, U and V channels */
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dma_addr_t sg_dma;
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struct pxa_cam_dma dmas[3];
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struct pxa_dma_desc *sg_cpu;
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size_t sg_size;
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int inwork;
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int inwork;
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enum pxa_camera_active_dma active_dma;
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};
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};
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struct pxa_framebuffer_queue {
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struct pxa_framebuffer_queue {
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@ -100,7 +117,8 @@ struct pxa_camera_dev {
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unsigned int irq;
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unsigned int irq;
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void __iomem *base;
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void __iomem *base;
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unsigned int dma_chan_y;
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unsigned int dma_chans[3];
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struct pxacamera_platform_data *pdata;
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struct pxacamera_platform_data *pdata;
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struct resource *res;
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struct resource *res;
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@ -128,7 +146,15 @@ static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
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dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
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dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
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*size = icd->width * icd->height * ((icd->current_fmt->depth + 7) >> 3);
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/* planar capture requires Y, U and V buffers to be page aligned */
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if (icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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*size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
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*size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
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*size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
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} else {
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*size = icd->width * icd->height *
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((icd->current_fmt->depth + 7) >> 3);
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}
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if (0 == *count)
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if (0 == *count)
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*count = 32;
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*count = 32;
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@ -145,6 +171,7 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
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to_soc_camera_host(icd->dev.parent);
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to_soc_camera_host(icd->dev.parent);
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_camera_dev *pcdev = ici->priv;
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struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
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struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
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int i;
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BUG_ON(in_interrupt());
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BUG_ON(in_interrupt());
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@ -157,14 +184,62 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
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videobuf_dma_unmap(vq, dma);
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videobuf_dma_unmap(vq, dma);
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videobuf_dma_free(dma);
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videobuf_dma_free(dma);
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if (buf->sg_cpu)
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for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
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dma_free_coherent(pcdev->dev, buf->sg_size, buf->sg_cpu,
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if (buf->dmas[i].sg_cpu)
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buf->sg_dma);
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dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
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buf->sg_cpu = NULL;
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buf->dmas[i].sg_cpu,
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buf->dmas[i].sg_dma);
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buf->dmas[i].sg_cpu = NULL;
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}
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buf->vb.state = VIDEOBUF_NEEDS_INIT;
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buf->vb.state = VIDEOBUF_NEEDS_INIT;
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}
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}
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static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
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struct pxa_buffer *buf,
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struct videobuf_dmabuf *dma, int channel,
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int sglen, int sg_start, int cibr,
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unsigned int size)
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{
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struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
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int i;
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if (pxa_dma->sg_cpu)
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dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
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pxa_dma->sg_cpu, pxa_dma->sg_dma);
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pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
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pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
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&pxa_dma->sg_dma, GFP_KERNEL);
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if (!pxa_dma->sg_cpu)
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return -ENOMEM;
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pxa_dma->sglen = sglen;
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for (i = 0; i < sglen; i++) {
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int sg_i = sg_start + i;
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struct scatterlist *sg = dma->sglist;
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unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
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pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
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pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
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/* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
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xfer_len = (min(dma_len, size) + 7) & ~7;
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pxa_dma->sg_cpu[i].dcmd =
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DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
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size -= dma_len;
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pxa_dma->sg_cpu[i].ddadr =
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pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
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}
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pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
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pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
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return 0;
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}
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static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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static int pxa_videobuf_prepare(struct videobuf_queue *vq,
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struct videobuf_buffer *vb, enum v4l2_field field)
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struct videobuf_buffer *vb, enum v4l2_field field)
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{
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{
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to_soc_camera_host(icd->dev.parent);
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to_soc_camera_host(icd->dev.parent);
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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int i, ret;
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int ret;
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int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
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int size_y, size_u = 0, size_v = 0;
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dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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vb, vb->baddr, vb->bsize);
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vb, vb->baddr, vb->bsize);
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if (ret)
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if (ret)
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goto fail;
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goto fail;
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if (buf->sg_cpu)
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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dma_free_coherent(pcdev->dev, buf->sg_size, buf->sg_cpu,
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/* FIXME the calculations should be more precise */
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buf->sg_dma);
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sglen_y = dma->sglen / 2;
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sglen_u = sglen_v = dma->sglen / 4 + 1;
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sglen_yu = sglen_y + sglen_u;
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size_y = size / 2;
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size_u = size_v = size / 4;
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} else {
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sglen_y = dma->sglen;
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size_y = size;
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}
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buf->sg_size = (dma->sglen + 1) * sizeof(struct pxa_dma_desc);
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/* init DMA for Y channel */
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buf->sg_cpu = dma_alloc_coherent(pcdev->dev, buf->sg_size,
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ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
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&buf->sg_dma, GFP_KERNEL);
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0, 0x28, size_y);
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if (!buf->sg_cpu) {
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ret = -ENOMEM;
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if (ret) {
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dev_err(pcdev->dev,
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"DMA initialization for Y/RGB failed\n");
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goto fail;
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goto fail;
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}
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}
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dev_dbg(&icd->dev, "nents=%d size: %d sg=0x%p\n",
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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dma->sglen, size, dma->sglist);
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/* init DMA for U channel */
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for (i = 0; i < dma->sglen; i++) {
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ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
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struct scatterlist *sg = dma->sglist;
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sglen_y, 0x30, size_u);
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unsigned int dma_len = sg_dma_len(&sg[i]), xfer_len;
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if (ret) {
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dev_err(pcdev->dev,
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"DMA initialization for U failed\n");
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goto fail_u;
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}
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/* CIBR0 */
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/* init DMA for V channel */
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buf->sg_cpu[i].dsadr = pcdev->res->start + 0x28;
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ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
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buf->sg_cpu[i].dtadr = sg_dma_address(&sg[i]);
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sglen_yu, 0x38, size_v);
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/* PXA270 Developer's Manual 27.4.4.1:
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if (ret) {
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* round up to 8 bytes */
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dev_err(pcdev->dev,
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xfer_len = (min(dma_len, size) + 7) & ~7;
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"DMA initialization for V failed\n");
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if (xfer_len & 7)
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goto fail_v;
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dev_err(&icd->dev, "Unaligned buffer: "
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}
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"dma_len %u, size %u\n", dma_len, size);
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buf->sg_cpu[i].dcmd = DCMD_FLOWSRC | DCMD_BURST8 |
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DCMD_INCTRGADDR | xfer_len;
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size -= dma_len;
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buf->sg_cpu[i].ddadr = buf->sg_dma + (i + 1) *
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sizeof(struct pxa_dma_desc);
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}
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}
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buf->sg_cpu[dma->sglen - 1].ddadr = DDADR_STOP;
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buf->sg_cpu[dma->sglen - 1].dcmd |= DCMD_ENDIRQEN;
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vb->state = VIDEOBUF_PREPARED;
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vb->state = VIDEOBUF_PREPARED;
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}
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}
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buf->inwork = 0;
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buf->inwork = 0;
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buf->active_dma = DMA_Y;
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
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buf->active_dma |= DMA_U | DMA_V;
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return 0;
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return 0;
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fail_v:
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dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
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buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
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fail_u:
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dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
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buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
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fail:
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fail:
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free_buffer(vq, buf);
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free_buffer(vq, buf);
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out:
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out:
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@ -277,8 +369,6 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_camera_dev *pcdev = ici->priv;
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
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struct pxa_buffer *active;
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struct pxa_buffer *active;
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struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
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int nents = dma->sglen;
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unsigned long flags;
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unsigned long flags;
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dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
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@ -292,59 +382,86 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
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if (!active) {
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if (!active) {
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CIFR |= CIFR_RESET_F;
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CIFR |= CIFR_RESET_F;
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DDADR(pcdev->dma_chan_y) = buf->sg_dma;
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DDADR(pcdev->dma_chans[0]) = buf->dmas[0].sg_dma;
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DCSR(pcdev->dma_chan_y) = DCSR_RUN;
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DCSR(pcdev->dma_chans[0]) = DCSR_RUN;
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
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DDADR(pcdev->dma_chans[1]) = buf->dmas[1].sg_dma;
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DCSR(pcdev->dma_chans[1]) = DCSR_RUN;
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DDADR(pcdev->dma_chans[2]) = buf->dmas[2].sg_dma;
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DCSR(pcdev->dma_chans[2]) = DCSR_RUN;
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}
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pcdev->active = buf;
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pcdev->active = buf;
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CICR0 |= CICR0_ENB;
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CICR0 |= CICR0_ENB;
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} else {
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} else {
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struct videobuf_dmabuf *active_dma =
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struct pxa_cam_dma *buf_dma;
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videobuf_to_dma(&active->vb);
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struct pxa_cam_dma *act_dma;
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/* Stop DMA engine */
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int channels = 1;
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DCSR(pcdev->dma_chan_y) = 0;
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int nents;
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int i;
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/* Add the descriptors we just initialized to the currently
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if (buf->fmt->fourcc == V4L2_PIX_FMT_YUV422P)
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* running chain
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channels = 3;
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*/
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active->sg_cpu[active_dma->sglen - 1].ddadr = buf->sg_dma;
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/* Setup a dummy descriptor with the DMA engines current
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for (i = 0; i < channels; i++) {
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* state
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buf_dma = &buf->dmas[i];
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*/
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act_dma = &active->dmas[i];
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/* CIBR0 */
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nents = buf_dma->sglen;
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buf->sg_cpu[nents].dsadr = pcdev->res->start + 0x28;
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buf->sg_cpu[nents].dtadr = DTADR(pcdev->dma_chan_y);
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buf->sg_cpu[nents].dcmd = DCMD(pcdev->dma_chan_y);
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if (DDADR(pcdev->dma_chan_y) == DDADR_STOP) {
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/* Stop DMA engine */
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/* The DMA engine is on the last descriptor, set the
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DCSR(pcdev->dma_chans[i]) = 0;
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* next descriptors address to the descriptors
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|
||||||
* we just initialized
|
/* Add the descriptors we just initialized to
|
||||||
|
the currently running chain */
|
||||||
|
act_dma->sg_cpu[act_dma->sglen - 1].ddadr =
|
||||||
|
buf_dma->sg_dma;
|
||||||
|
|
||||||
|
/* Setup a dummy descriptor with the DMA engines current
|
||||||
|
* state
|
||||||
*/
|
*/
|
||||||
buf->sg_cpu[nents].ddadr = buf->sg_dma;
|
buf_dma->sg_cpu[nents].dsadr =
|
||||||
} else {
|
pcdev->res->start + 0x28 + i*8; /* CIBRx */
|
||||||
buf->sg_cpu[nents].ddadr = DDADR(pcdev->dma_chan_y);
|
buf_dma->sg_cpu[nents].dtadr =
|
||||||
|
DTADR(pcdev->dma_chans[i]);
|
||||||
|
buf_dma->sg_cpu[nents].dcmd =
|
||||||
|
DCMD(pcdev->dma_chans[i]);
|
||||||
|
|
||||||
|
if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
|
||||||
|
/* The DMA engine is on the last
|
||||||
|
descriptor, set the next descriptors
|
||||||
|
address to the descriptors we just
|
||||||
|
initialized */
|
||||||
|
buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
|
||||||
|
} else {
|
||||||
|
buf_dma->sg_cpu[nents].ddadr =
|
||||||
|
DDADR(pcdev->dma_chans[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The next descriptor is the dummy descriptor */
|
||||||
|
DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
|
||||||
|
sizeof(struct pxa_dma_desc);
|
||||||
|
|
||||||
|
DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The next descriptor is the dummy descriptor */
|
|
||||||
DDADR(pcdev->dma_chan_y) = buf->sg_dma + nents *
|
|
||||||
sizeof(struct pxa_dma_desc);
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
if (CISR & CISR_IFO_0) {
|
if (CISR & (CISR_IFO_0 | CISR_IFO_1 | CISR_IFO_2)) {
|
||||||
dev_warn(pcdev->dev, "FIFO overrun\n");
|
dev_warn(pcdev->dev, "FIFO overrun\n");
|
||||||
DDADR(pcdev->dma_chan_y) = pcdev->active->sg_dma;
|
for (i = 0; i < channels; i++)
|
||||||
|
DDADR(pcdev->dma_chans[i]) =
|
||||||
|
pcdev->active->dmas[i].sg_dma;
|
||||||
|
|
||||||
CICR0 &= ~CICR0_ENB;
|
CICR0 &= ~CICR0_ENB;
|
||||||
CIFR |= CIFR_RESET_F;
|
CIFR |= CIFR_RESET_F;
|
||||||
DCSR(pcdev->dma_chan_y) = DCSR_RUN;
|
for (i = 0; i < channels; i++)
|
||||||
|
DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
|
||||||
CICR0 |= CICR0_ENB;
|
CICR0 |= CICR0_ENB;
|
||||||
} else
|
}
|
||||||
#endif
|
#endif
|
||||||
DCSR(pcdev->dma_chan_y) = DCSR_RUN;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
spin_unlock_irqrestore(&pcdev->lock, flags);
|
spin_unlock_irqrestore(&pcdev->lock, flags);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void pxa_videobuf_release(struct videobuf_queue *vq,
|
static void pxa_videobuf_release(struct videobuf_queue *vq,
|
||||||
|
@ -376,9 +493,33 @@ static void pxa_videobuf_release(struct videobuf_queue *vq,
|
||||||
free_buffer(vq, buf);
|
free_buffer(vq, buf);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void pxa_camera_dma_irq_y(int channel, void *data)
|
static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
|
||||||
|
struct videobuf_buffer *vb,
|
||||||
|
struct pxa_buffer *buf)
|
||||||
|
{
|
||||||
|
/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
|
||||||
|
list_del_init(&vb->queue);
|
||||||
|
vb->state = VIDEOBUF_DONE;
|
||||||
|
do_gettimeofday(&vb->ts);
|
||||||
|
vb->field_count++;
|
||||||
|
wake_up(&vb->done);
|
||||||
|
|
||||||
|
if (list_empty(&pcdev->capture)) {
|
||||||
|
pcdev->active = NULL;
|
||||||
|
DCSR(pcdev->dma_chans[0]) = 0;
|
||||||
|
DCSR(pcdev->dma_chans[1]) = 0;
|
||||||
|
DCSR(pcdev->dma_chans[2]) = 0;
|
||||||
|
CICR0 &= ~CICR0_ENB;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
pcdev->active = list_entry(pcdev->capture.next,
|
||||||
|
struct pxa_buffer, vb.queue);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
|
||||||
|
enum pxa_camera_active_dma act_dma)
|
||||||
{
|
{
|
||||||
struct pxa_camera_dev *pcdev = data;
|
|
||||||
struct pxa_buffer *buf;
|
struct pxa_buffer *buf;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned int status;
|
unsigned int status;
|
||||||
|
@ -386,8 +527,8 @@ static void pxa_camera_dma_irq_y(int channel, void *data)
|
||||||
|
|
||||||
spin_lock_irqsave(&pcdev->lock, flags);
|
spin_lock_irqsave(&pcdev->lock, flags);
|
||||||
|
|
||||||
status = DCSR(pcdev->dma_chan_y);
|
status = DCSR(channel);
|
||||||
DCSR(pcdev->dma_chan_y) = status;
|
DCSR(channel) = status | DCSR_ENDINTR;
|
||||||
|
|
||||||
if (status & DCSR_BUSERR) {
|
if (status & DCSR_BUSERR) {
|
||||||
dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
|
dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
|
||||||
|
@ -411,27 +552,32 @@ static void pxa_camera_dma_irq_y(int channel, void *data)
|
||||||
dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
|
dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
|
||||||
vb, vb->baddr, vb->bsize);
|
vb, vb->baddr, vb->bsize);
|
||||||
|
|
||||||
/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
|
buf->active_dma &= ~act_dma;
|
||||||
list_del_init(&vb->queue);
|
if (!buf->active_dma)
|
||||||
vb->state = VIDEOBUF_DONE;
|
pxa_camera_wakeup(pcdev, vb, buf);
|
||||||
do_gettimeofday(&vb->ts);
|
|
||||||
vb->field_count++;
|
|
||||||
wake_up(&vb->done);
|
|
||||||
|
|
||||||
if (list_empty(&pcdev->capture)) {
|
|
||||||
pcdev->active = NULL;
|
|
||||||
DCSR(pcdev->dma_chan_y) = 0;
|
|
||||||
CICR0 &= ~CICR0_ENB;
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
|
|
||||||
pcdev->active = list_entry(pcdev->capture.next, struct pxa_buffer,
|
|
||||||
vb.queue);
|
|
||||||
|
|
||||||
out:
|
out:
|
||||||
spin_unlock_irqrestore(&pcdev->lock, flags);
|
spin_unlock_irqrestore(&pcdev->lock, flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void pxa_camera_dma_irq_y(int channel, void *data)
|
||||||
|
{
|
||||||
|
struct pxa_camera_dev *pcdev = data;
|
||||||
|
pxa_camera_dma_irq(channel, pcdev, DMA_Y);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pxa_camera_dma_irq_u(int channel, void *data)
|
||||||
|
{
|
||||||
|
struct pxa_camera_dev *pcdev = data;
|
||||||
|
pxa_camera_dma_irq(channel, pcdev, DMA_U);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pxa_camera_dma_irq_v(int channel, void *data)
|
||||||
|
{
|
||||||
|
struct pxa_camera_dev *pcdev = data;
|
||||||
|
pxa_camera_dma_irq(channel, pcdev, DMA_V);
|
||||||
|
}
|
||||||
|
|
||||||
static struct videobuf_queue_ops pxa_videobuf_ops = {
|
static struct videobuf_queue_ops pxa_videobuf_ops = {
|
||||||
.buf_setup = pxa_videobuf_setup,
|
.buf_setup = pxa_videobuf_setup,
|
||||||
.buf_prepare = pxa_videobuf_prepare,
|
.buf_prepare = pxa_videobuf_prepare,
|
||||||
|
@ -525,7 +671,6 @@ static irqreturn_t pxa_camera_irq(int irq, void *data)
|
||||||
dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
|
dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
|
||||||
|
|
||||||
CISR = status;
|
CISR = status;
|
||||||
|
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -571,8 +716,11 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd)
|
||||||
|
|
||||||
/* disable capture, disable interrupts */
|
/* disable capture, disable interrupts */
|
||||||
CICR0 = 0x3ff;
|
CICR0 = 0x3ff;
|
||||||
|
|
||||||
/* Stop DMA engine */
|
/* Stop DMA engine */
|
||||||
DCSR(pcdev->dma_chan_y) = 0;
|
DCSR(pcdev->dma_chans[0]) = 0;
|
||||||
|
DCSR(pcdev->dma_chans[1]) = 0;
|
||||||
|
DCSR(pcdev->dma_chans[2]) = 0;
|
||||||
|
|
||||||
icd->ops->release(icd);
|
icd->ops->release(icd);
|
||||||
|
|
||||||
|
@ -625,7 +773,7 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
|
||||||
to_soc_camera_host(icd->dev.parent);
|
to_soc_camera_host(icd->dev.parent);
|
||||||
struct pxa_camera_dev *pcdev = ici->priv;
|
struct pxa_camera_dev *pcdev = ici->priv;
|
||||||
unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
|
unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
|
||||||
u32 cicr0, cicr4 = 0;
|
u32 cicr0, cicr1, cicr4 = 0;
|
||||||
int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
|
int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
|
||||||
|
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
|
@ -702,7 +850,25 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
|
||||||
cicr0 = CICR0;
|
cicr0 = CICR0;
|
||||||
if (cicr0 & CICR0_ENB)
|
if (cicr0 & CICR0_ENB)
|
||||||
CICR0 = cicr0 & ~CICR0_ENB;
|
CICR0 = cicr0 & ~CICR0_ENB;
|
||||||
CICR1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
|
|
||||||
|
cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
|
||||||
|
|
||||||
|
switch (pixfmt) {
|
||||||
|
case V4L2_PIX_FMT_YUV422P:
|
||||||
|
cicr1 |= CICR1_YCBCR_F;
|
||||||
|
case V4L2_PIX_FMT_YUYV:
|
||||||
|
cicr1 |= CICR1_COLOR_SP_VAL(2);
|
||||||
|
break;
|
||||||
|
case V4L2_PIX_FMT_RGB555:
|
||||||
|
cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
|
||||||
|
CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
|
||||||
|
break;
|
||||||
|
case V4L2_PIX_FMT_RGB565:
|
||||||
|
cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
CICR1 = cicr1;
|
||||||
CICR2 = 0;
|
CICR2 = 0;
|
||||||
CICR3 = CICR3_LPF_VAL(icd->height - 1) |
|
CICR3 = CICR3_LPF_VAL(icd->height - 1) |
|
||||||
CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
|
CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
|
||||||
|
@ -905,16 +1071,36 @@ static int pxa_camera_probe(struct platform_device *pdev)
|
||||||
pcdev->dev = &pdev->dev;
|
pcdev->dev = &pdev->dev;
|
||||||
|
|
||||||
/* request dma */
|
/* request dma */
|
||||||
pcdev->dma_chan_y = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
|
pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
|
||||||
pxa_camera_dma_irq_y, pcdev);
|
pxa_camera_dma_irq_y, pcdev);
|
||||||
if (pcdev->dma_chan_y < 0) {
|
if (pcdev->dma_chans[0] < 0) {
|
||||||
dev_err(pcdev->dev, "Can't request DMA for Y\n");
|
dev_err(pcdev->dev, "Can't request DMA for Y\n");
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
goto exit_iounmap;
|
goto exit_iounmap;
|
||||||
}
|
}
|
||||||
dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chan_y);
|
dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
|
||||||
|
|
||||||
DRCMR68 = pcdev->dma_chan_y | DRCMR_MAPVLD;
|
pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
|
||||||
|
pxa_camera_dma_irq_u, pcdev);
|
||||||
|
if (pcdev->dma_chans[1] < 0) {
|
||||||
|
dev_err(pcdev->dev, "Can't request DMA for U\n");
|
||||||
|
err = -ENOMEM;
|
||||||
|
goto exit_free_dma_y;
|
||||||
|
}
|
||||||
|
dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
|
||||||
|
|
||||||
|
pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
|
||||||
|
pxa_camera_dma_irq_v, pcdev);
|
||||||
|
if (pcdev->dma_chans[0] < 0) {
|
||||||
|
dev_err(pcdev->dev, "Can't request DMA for V\n");
|
||||||
|
err = -ENOMEM;
|
||||||
|
goto exit_free_dma_u;
|
||||||
|
}
|
||||||
|
dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
|
||||||
|
|
||||||
|
DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
|
||||||
|
DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
|
||||||
|
DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
|
||||||
|
|
||||||
/* request irq */
|
/* request irq */
|
||||||
err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
|
err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
|
||||||
|
@ -936,7 +1122,11 @@ static int pxa_camera_probe(struct platform_device *pdev)
|
||||||
exit_free_irq:
|
exit_free_irq:
|
||||||
free_irq(pcdev->irq, pcdev);
|
free_irq(pcdev->irq, pcdev);
|
||||||
exit_free_dma:
|
exit_free_dma:
|
||||||
pxa_free_dma(pcdev->dma_chan_y);
|
pxa_free_dma(pcdev->dma_chans[2]);
|
||||||
|
exit_free_dma_u:
|
||||||
|
pxa_free_dma(pcdev->dma_chans[1]);
|
||||||
|
exit_free_dma_y:
|
||||||
|
pxa_free_dma(pcdev->dma_chans[0]);
|
||||||
exit_iounmap:
|
exit_iounmap:
|
||||||
iounmap(base);
|
iounmap(base);
|
||||||
exit_release:
|
exit_release:
|
||||||
|
@ -956,7 +1146,9 @@ static int __devexit pxa_camera_remove(struct platform_device *pdev)
|
||||||
|
|
||||||
clk_put(pcdev->clk);
|
clk_put(pcdev->clk);
|
||||||
|
|
||||||
pxa_free_dma(pcdev->dma_chan_y);
|
pxa_free_dma(pcdev->dma_chans[0]);
|
||||||
|
pxa_free_dma(pcdev->dma_chans[1]);
|
||||||
|
pxa_free_dma(pcdev->dma_chans[2]);
|
||||||
free_irq(pcdev->irq, pcdev);
|
free_irq(pcdev->irq, pcdev);
|
||||||
|
|
||||||
soc_camera_host_unregister(&pxa_soc_camera_host);
|
soc_camera_host_unregister(&pxa_soc_camera_host);
|
||||||
|
|
Loading…
Reference in New Issue