spi: mediatek: Add spi bus for Mediatek MT8173
This patch adds basic spi bus for MT8173. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>hifive-unleashed-5.1
Leilk Liu
Mark Brown
parent
0d850e7cdc
commit
a568231f46
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@ -326,6 +326,15 @@ config SPI_MESON_SPIFC
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This enables master mode support for the SPIFC (SPI flash
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controller) available in Amlogic Meson SoCs.
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config SPI_MT65XX
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tristate "MediaTek SPI controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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help
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This selects the MediaTek(R) SPI bus driver.
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If you want to use MediaTek(R) SPI interface,
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say Y or M here.If you are not sure, say N.
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SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
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config SPI_OC_TINY
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tristate "OpenCores tiny SPI"
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depends on GPIOLIB || COMPILE_TEST
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@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
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obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
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obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
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obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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@ -0,0 +1,749 @@
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Leilk Liu <leilk.liu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/spi-mt65xx.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#define SPI_CFG0_REG 0x0000
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#define SPI_CFG1_REG 0x0004
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#define SPI_TX_SRC_REG 0x0008
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#define SPI_RX_DST_REG 0x000c
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#define SPI_TX_DATA_REG 0x0010
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#define SPI_RX_DATA_REG 0x0014
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#define SPI_CMD_REG 0x0018
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#define SPI_STATUS0_REG 0x001c
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CMD_ACT_OFFSET 0
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#define SPI_CMD_RESUME_OFFSET 1
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#define SPI_CMD_CPHA_OFFSET 8
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#define SPI_CMD_CPOL_OFFSET 9
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#define SPI_CMD_TXMSBF_OFFSET 12
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#define SPI_CMD_RXMSBF_OFFSET 13
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#define SPI_CMD_RX_ENDIAN_OFFSET 14
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#define SPI_CMD_TX_ENDIAN_OFFSET 15
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
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#define SPI_CMD_TX_DMA BIT(11)
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#define SPI_CMD_TXMSBF BIT(12)
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#define SPI_CMD_RXMSBF BIT(13)
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#define SPI_CMD_RX_ENDIAN BIT(14)
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define MTK_SPI_QUIRK_PAD_SELECT 1
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/* Must explicitly send dummy Tx bytes to do Rx only transfer */
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#define MTK_SPI_QUIRK_MUST_TX 1
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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#define MTK_SPI_MAX_FIFO_SIZE 32
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#define MTK_SPI_PACKET_SIZE 1024
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struct mtk_spi_compatible {
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u32 need_pad_sel;
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u32 must_tx;
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};
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struct mtk_spi {
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void __iomem *base;
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u32 state;
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u32 pad_sel;
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struct clk *spi_clk, *parent_clk;
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struct spi_transfer *cur_transfer;
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u32 xfer_len;
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struct scatterlist *tx_sgl, *rx_sgl;
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u32 tx_sgl_len, rx_sgl_len;
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const struct mtk_spi_compatible *dev_comp;
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};
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static const struct mtk_spi_compatible mt6589_compat = {
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.need_pad_sel = 0,
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.must_tx = 0,
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};
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static const struct mtk_spi_compatible mt8135_compat = {
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.need_pad_sel = 0,
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.must_tx = 0,
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};
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static const struct mtk_spi_compatible mt8173_compat = {
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.need_pad_sel = MTK_SPI_QUIRK_PAD_SELECT,
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.must_tx = MTK_SPI_QUIRK_MUST_TX,
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};
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/*
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* A piece of default chip info unless the platform
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* supplies it.
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*/
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static const struct mtk_chip_config mtk_default_chip_info = {
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.rx_mlsb = 1,
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.tx_mlsb = 1,
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.tx_endian = 0,
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.rx_endian = 0,
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};
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static const struct of_device_id mtk_spi_of_match[] = {
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{ .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
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{ .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
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{ .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
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static void mtk_spi_reset(struct mtk_spi *mdata)
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{
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u32 reg_val;
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/* set the software reset bit in SPI_CMD_REG. */
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val |= SPI_CMD_RST;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~SPI_CMD_RST;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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}
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static void mtk_spi_config(struct mtk_spi *mdata,
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struct mtk_chip_config *chip_config)
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{
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u32 reg_val;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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/* set the mlsbx and mlsbtx */
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reg_val &= ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF);
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reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET);
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reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET);
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/* set the tx/rx endian */
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reg_val &= ~(SPI_CMD_TX_ENDIAN | SPI_CMD_RX_ENDIAN);
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reg_val |= (chip_config->tx_endian << SPI_CMD_TX_ENDIAN_OFFSET);
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reg_val |= (chip_config->rx_endian << SPI_CMD_RX_ENDIAN_OFFSET);
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/* set finish and pause interrupt always enable */
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reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
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/* disable dma mode */
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reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
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/* disable deassert mode */
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reg_val &= ~SPI_CMD_DEASSERT;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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/* pad select */
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if (mdata->dev_comp->need_pad_sel)
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writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
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}
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static int mtk_spi_prepare_hardware(struct spi_master *master)
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{
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struct spi_transfer *trans;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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struct spi_message *msg = master->cur_msg;
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int ret;
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ret = clk_prepare_enable(mdata->spi_clk);
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if (ret < 0) {
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dev_err(&master->dev, "failed to enable clock (%d)\n", ret);
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return ret;
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}
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trans = list_first_entry(&msg->transfers, struct spi_transfer,
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transfer_list);
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if (trans->cs_change == 0) {
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mdata->state = MTK_SPI_IDLE;
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mtk_spi_reset(mdata);
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}
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return ret;
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}
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static int mtk_spi_unprepare_hardware(struct spi_master *master)
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{
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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clk_disable_unprepare(mdata->spi_clk);
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return 0;
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}
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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u32 reg_val;
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u8 cpha, cpol;
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struct mtk_chip_config *chip_config;
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struct spi_device *spi = msg->spi;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~(SPI_CMD_CPHA | SPI_CMD_CPOL);
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reg_val |= (cpha << SPI_CMD_CPHA_OFFSET);
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reg_val |= (cpol << SPI_CMD_CPOL_OFFSET);
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writel(reg_val, mdata->base + SPI_CMD_REG);
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chip_config = spi->controller_data;
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if (!chip_config) {
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chip_config = (void *)&mtk_default_chip_info;
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spi->controller_data = chip_config;
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}
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mtk_spi_config(mdata, chip_config);
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return 0;
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}
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static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
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{
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u32 reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (!enable)
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reg_val |= SPI_CMD_PAUSE_EN;
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else
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reg_val &= ~SPI_CMD_PAUSE_EN;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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}
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static void mtk_spi_prepare_transfer(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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u32 spi_clk_hz, div, high_time, low_time, holdtime,
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setuptime, cs_idletime, reg_val = 0;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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spi_clk_hz = clk_get_rate(mdata->spi_clk);
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if (xfer->speed_hz < spi_clk_hz / 2)
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div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
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else
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div = 1;
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high_time = (div + 1) / 2;
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low_time = (div + 1) / 2;
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holdtime = (div + 1) / 2 * 2;
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setuptime = (div + 1) / 2 * 2;
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cs_idletime = (div + 1) / 2 * 2;
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reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
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reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
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reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
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reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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static void mtk_spi_setup_packet(struct spi_master *master)
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{
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u32 packet_size, packet_loop, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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packet_size = min_t(unsigned, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
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packet_loop = mdata->xfer_len / packet_size;
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK);
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reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
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reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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static void mtk_spi_enable_transfer(struct spi_master *master)
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{
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int cmd;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cmd = readl(mdata->base + SPI_CMD_REG);
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if (mdata->state == MTK_SPI_IDLE)
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cmd |= 1 << SPI_CMD_ACT_OFFSET;
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else
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cmd |= 1 << SPI_CMD_RESUME_OFFSET;
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writel(cmd, mdata->base + SPI_CMD_REG);
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}
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static int mtk_spi_get_mult_delta(int xfer_len)
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{
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int mult_delta;
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if (xfer_len > MTK_SPI_PACKET_SIZE)
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mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
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else
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mult_delta = 0;
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return mult_delta;
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}
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static void mtk_spi_update_mdata_len(struct spi_master *master)
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{
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int mult_delta;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
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if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
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mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
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mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
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mdata->rx_sgl_len = mult_delta;
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mdata->tx_sgl_len -= mdata->xfer_len;
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} else {
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mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
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mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
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mdata->tx_sgl_len = mult_delta;
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mdata->rx_sgl_len -= mdata->xfer_len;
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}
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} else if (mdata->tx_sgl_len) {
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mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
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mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
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mdata->tx_sgl_len = mult_delta;
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} else if (mdata->rx_sgl_len) {
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mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
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mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
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mdata->rx_sgl_len = mult_delta;
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}
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}
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static void mtk_spi_setup_dma_addr(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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if (mdata->tx_sgl)
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writel(cpu_to_le32(xfer->tx_dma), mdata->base + SPI_TX_SRC_REG);
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if (mdata->rx_sgl)
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writel(cpu_to_le32(xfer->rx_dma), mdata->base + SPI_RX_DST_REG);
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}
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static int mtk_spi_fifo_transfer(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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int cnt, i;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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mdata->cur_transfer = xfer;
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mdata->xfer_len = xfer->len;
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mtk_spi_prepare_transfer(master, xfer);
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mtk_spi_setup_packet(master);
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if (xfer->len % 4)
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cnt = xfer->len / 4 + 1;
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else
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cnt = xfer->len / 4;
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for (i = 0; i < cnt; i++)
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writel(*((u32 *)xfer->tx_buf + i),
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mdata->base + SPI_TX_DATA_REG);
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mtk_spi_enable_transfer(master);
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return 1;
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}
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|
||||
static int mtk_spi_dma_transfer(struct spi_master *master,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
int cmd;
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
mdata->tx_sgl = NULL;
|
||||
mdata->rx_sgl = NULL;
|
||||
mdata->tx_sgl_len = 0;
|
||||
mdata->rx_sgl_len = 0;
|
||||
mdata->cur_transfer = xfer;
|
||||
|
||||
mtk_spi_prepare_transfer(master, xfer);
|
||||
|
||||
cmd = readl(mdata->base + SPI_CMD_REG);
|
||||
if (xfer->tx_buf)
|
||||
cmd |= SPI_CMD_TX_DMA;
|
||||
if (xfer->rx_buf)
|
||||
cmd |= SPI_CMD_RX_DMA;
|
||||
writel(cmd, mdata->base + SPI_CMD_REG);
|
||||
|
||||
if (xfer->tx_buf)
|
||||
mdata->tx_sgl = xfer->tx_sg.sgl;
|
||||
if (xfer->rx_buf)
|
||||
mdata->rx_sgl = xfer->rx_sg.sgl;
|
||||
|
||||
if (mdata->tx_sgl) {
|
||||
xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
|
||||
mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
|
||||
}
|
||||
if (mdata->rx_sgl) {
|
||||
xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
|
||||
mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
|
||||
}
|
||||
|
||||
mtk_spi_update_mdata_len(master);
|
||||
mtk_spi_setup_packet(master);
|
||||
mtk_spi_setup_dma_addr(master, xfer);
|
||||
mtk_spi_enable_transfer(master);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int mtk_spi_transfer_one(struct spi_master *master,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
if (master->can_dma(master, spi, xfer))
|
||||
return mtk_spi_dma_transfer(master, spi, xfer);
|
||||
else
|
||||
return mtk_spi_fifo_transfer(master, spi, xfer);
|
||||
}
|
||||
|
||||
static bool mtk_spi_can_dma(struct spi_master *master,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
|
||||
}
|
||||
|
||||
static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
u32 cmd, reg_val, i;
|
||||
struct spi_master *master = dev_id;
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
struct spi_transfer *trans = mdata->cur_transfer;
|
||||
|
||||
reg_val = readl(mdata->base + SPI_STATUS0_REG);
|
||||
if (reg_val & 0x2)
|
||||
mdata->state = MTK_SPI_PAUSED;
|
||||
else
|
||||
mdata->state = MTK_SPI_IDLE;
|
||||
|
||||
if (!master->can_dma(master, master->cur_msg->spi, trans)) {
|
||||
/* xfer len is not N*4 bytes every time in a transfer,
|
||||
* but SPI_RX_DATA_REG must reads 4 bytes once,
|
||||
* so rx buffer byte by byte.
|
||||
*/
|
||||
if (trans->rx_buf) {
|
||||
for (i = 0; i < mdata->xfer_len; i++) {
|
||||
if (i % 4 == 0)
|
||||
reg_val =
|
||||
readl(mdata->base + SPI_RX_DATA_REG);
|
||||
*((u8 *)(trans->rx_buf + i)) =
|
||||
(reg_val >> ((i % 4) * 8)) & 0xff;
|
||||
}
|
||||
}
|
||||
spi_finalize_current_transfer(master);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
if (mdata->tx_sgl)
|
||||
trans->tx_dma += mdata->xfer_len;
|
||||
if (mdata->rx_sgl)
|
||||
trans->rx_dma += mdata->xfer_len;
|
||||
|
||||
if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
|
||||
mdata->tx_sgl = sg_next(mdata->tx_sgl);
|
||||
if (mdata->tx_sgl) {
|
||||
trans->tx_dma = sg_dma_address(mdata->tx_sgl);
|
||||
mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
|
||||
}
|
||||
}
|
||||
if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
|
||||
mdata->rx_sgl = sg_next(mdata->rx_sgl);
|
||||
if (mdata->rx_sgl) {
|
||||
trans->rx_dma = sg_dma_address(mdata->rx_sgl);
|
||||
mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
|
||||
}
|
||||
}
|
||||
|
||||
if (!mdata->tx_sgl && !mdata->rx_sgl) {
|
||||
/* spi disable dma */
|
||||
cmd = readl(mdata->base + SPI_CMD_REG);
|
||||
cmd &= ~SPI_CMD_TX_DMA;
|
||||
cmd &= ~SPI_CMD_RX_DMA;
|
||||
writel(cmd, mdata->base + SPI_CMD_REG);
|
||||
|
||||
spi_finalize_current_transfer(master);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
mtk_spi_update_mdata_len(master);
|
||||
mtk_spi_setup_packet(master);
|
||||
mtk_spi_setup_dma_addr(master, trans);
|
||||
mtk_spi_enable_transfer(master);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mtk_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct mtk_spi *mdata;
|
||||
const struct of_device_id *of_id;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
|
||||
if (!master) {
|
||||
dev_err(&pdev->dev, "failed to alloc spi master\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
master->auto_runtime_pm = true;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
|
||||
master->set_cs = mtk_spi_set_cs;
|
||||
master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
|
||||
master->unprepare_transfer_hardware = mtk_spi_unprepare_hardware;
|
||||
master->prepare_message = mtk_spi_prepare_message;
|
||||
master->transfer_one = mtk_spi_transfer_one;
|
||||
master->can_dma = mtk_spi_can_dma;
|
||||
|
||||
of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
|
||||
if (!of_id) {
|
||||
dev_err(&pdev->dev, "failed to probe of_node\n");
|
||||
ret = -EINVAL;
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
mdata = spi_master_get_devdata(master);
|
||||
mdata->dev_comp = of_id->data;
|
||||
if (mdata->dev_comp->must_tx)
|
||||
master->flags = SPI_MASTER_MUST_TX;
|
||||
|
||||
if (mdata->dev_comp->need_pad_sel) {
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"mediatek,pad-select",
|
||||
&mdata->pad_sel);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to read pad select: %d\n",
|
||||
ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
|
||||
dev_err(&pdev->dev, "wrong pad-select: %u\n",
|
||||
mdata->pad_sel);
|
||||
ret = -EINVAL;
|
||||
goto err_put_master;
|
||||
}
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
ret = -ENODEV;
|
||||
dev_err(&pdev->dev, "failed to determine base address\n");
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
mdata->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mdata->base)) {
|
||||
ret = PTR_ERR(mdata->base);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
|
||||
ret = irq;
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
if (!pdev->dev.dma_mask)
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
|
||||
IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
|
||||
if (IS_ERR(mdata->spi_clk)) {
|
||||
ret = PTR_ERR(mdata->spi_clk);
|
||||
dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
|
||||
if (IS_ERR(mdata->parent_clk)) {
|
||||
ret = PTR_ERR(mdata->parent_clk);
|
||||
dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(mdata->spi_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
err_put_master:
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
mtk_spi_reset(mdata);
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
spi_master_put(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int mtk_spi_suspend(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
ret = spi_master_suspend(master);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!pm_runtime_suspended(dev))
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_spi_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
ret = clk_prepare_enable(mdata->spi_clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_master_resume(master);
|
||||
if (ret < 0)
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int mtk_spi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
clk_disable_unprepare(mdata->spi_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_spi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
return clk_prepare_enable(mdata->spi_clk);
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static const struct dev_pm_ops mtk_spi_pm = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
|
||||
SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
|
||||
mtk_spi_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
struct platform_driver mtk_spi_driver = {
|
||||
.driver = {
|
||||
.name = "mtk-spi",
|
||||
.pm = &mtk_spi_pm,
|
||||
.of_match_table = mtk_spi_of_match,
|
||||
},
|
||||
.probe = mtk_spi_probe,
|
||||
.remove = mtk_spi_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(mtk_spi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("MTK SPI Controller driver");
|
||||
MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform: mtk_spi");
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* MTK SPI bus driver definitions
|
||||
*
|
||||
* Copyright (c) 2015 MediaTek Inc.
|
||||
* Author: Leilk Liu <leilk.liu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||
#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||
|
||||
/* Board specific platform_data */
|
||||
struct mtk_chip_config {
|
||||
u32 tx_mlsb;
|
||||
u32 rx_mlsb;
|
||||
u32 tx_endian;
|
||||
u32 rx_endian;
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue