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drm/i915: Explain why we need to write DPLL twice

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... it's because setting the Pixel Multiply bits only takes effect once
the PLL is enabled and stable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-12-03 21:13:16 +00:00
parent 17fe698110
commit a589b9f429
1 changed files with 5 additions and 5 deletions
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10
drivers/gpu/drm/i915/intel_display.c
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@ -4089,13 +4089,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
}
I915_WRITE(DPLL_MD(pipe), temp);
} else {
/* write it again -- the BIOS does, after all */
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
*
* So write it again.
*/
I915_WRITE(dpll_reg, dpll);
}
/* Wait for the clocks to stabilize. */
POSTING_READ(dpll_reg);
udelay(150);
}
intel_crtc->lowfreq_avail = false;