ARM: imx: pllv1: Fix PLL calculation for i.MX27
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This is a just sign bit. This patch makes different calculation for i.MX27. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>hifive-unleashed-5.1
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630a212501
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a594790368
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@ -18,6 +18,11 @@
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*
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*
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* PLL clock version 1, found on i.MX1/21/25/27/31/35
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* PLL clock version 1, found on i.MX1/21/25/27/31/35
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*/
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*/
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#define MFN_BITS (10)
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#define MFN_SIGN (BIT(MFN_BITS - 1))
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#define MFN_MASK (MFN_SIGN - 1)
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struct clk_pllv1 {
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struct clk_pllv1 {
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struct clk_hw hw;
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struct clk_hw hw;
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void __iomem *base;
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void __iomem *base;
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@ -25,6 +30,11 @@ struct clk_pllv1 {
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#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
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#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
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static inline bool mfn_is_negative(unsigned int mfn)
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{
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return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
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}
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static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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{
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@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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/*
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/*
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* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
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* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
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* 2's complements number
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* 2's complements number.
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* On i.MX27 the bit 9 is the sign bit.
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*/
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*/
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if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
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if (mfn_is_negative(mfn)) {
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mfn_abs = 0x400 - mfn;
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if (cpu_is_mx27())
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mfn_abs = mfn & MFN_MASK;
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else
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mfn_abs = BIT(MFN_BITS) - mfn;
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}
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rate = parent_rate * 2;
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rate = parent_rate * 2;
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rate /= pd + 1;
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rate /= pd + 1;
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@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
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do_div(ll, mfd + 1);
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do_div(ll, mfd + 1);
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if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
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if (mfn_is_negative(mfn))
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ll = -ll;
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ll = -ll;
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ll = (rate * mfi) + ll;
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ll = (rate * mfi) + ll;
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