drm/i915: Disable/enable planes as the first/last thing during modeset on ILK+
We already do this for HSW, but doing it makes sense for everything else as well. Extend it for ILK/SNB/IVB since that's where the new watermark code is used. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77297 [danvet: Resolve conflict since I've plucked this out of the middle of Ville's series.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3636,6 +3636,46 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
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hsw_enable_ips(intel_crtc);
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}
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static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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intel_enable_primary_hw_plane(dev_priv, plane, pipe);
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intel_enable_planes(crtc);
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intel_crtc_update_cursor(crtc, true);
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hsw_enable_ips(intel_crtc);
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mutex_lock(&dev->struct_mutex);
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intel_update_fbc(dev);
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mutex_unlock(&dev->struct_mutex);
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}
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static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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intel_crtc_wait_for_pending_flips(crtc);
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drm_vblank_off(dev, pipe);
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if (dev_priv->fbc.plane == plane)
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intel_disable_fbc(dev);
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hsw_disable_ips(intel_crtc);
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intel_crtc_update_cursor(crtc, false);
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intel_disable_planes(crtc);
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intel_disable_primary_hw_plane(dev_priv, plane, pipe);
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}
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static void ironlake_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@ -3643,7 +3683,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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WARN_ON(!crtc->enabled);
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@ -3679,23 +3718,18 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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intel_update_watermarks(crtc);
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intel_enable_pipe(intel_crtc);
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intel_enable_primary_hw_plane(dev_priv, plane, pipe);
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intel_enable_planes(crtc);
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intel_crtc_update_cursor(crtc, true);
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if (intel_crtc->config.has_pch_encoder)
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ironlake_pch_enable(crtc);
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mutex_lock(&dev->struct_mutex);
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intel_update_fbc(dev);
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mutex_unlock(&dev->struct_mutex);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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encoder->enable(encoder);
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if (HAS_PCH_CPT(dev))
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cpt_verify_modeset(dev, intel_crtc->pipe);
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ilk_crtc_enable_planes(crtc);
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/*
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* There seems to be a race in PCH platform hw (at least on some
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* outputs) where an enabled pipe still completes any pageflip right
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@ -3713,47 +3747,6 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
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return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
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}
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static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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intel_enable_primary_hw_plane(dev_priv, plane, pipe);
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intel_enable_planes(crtc);
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intel_crtc_update_cursor(crtc, true);
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hsw_enable_ips(intel_crtc);
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mutex_lock(&dev->struct_mutex);
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intel_update_fbc(dev);
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mutex_unlock(&dev->struct_mutex);
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}
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static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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intel_crtc_wait_for_pending_flips(crtc);
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drm_vblank_off(dev, pipe);
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/* FBC must be disabled before disabling the plane on HSW. */
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if (dev_priv->fbc.plane == plane)
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intel_disable_fbc(dev);
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hsw_disable_ips(intel_crtc);
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intel_crtc_update_cursor(crtc, false);
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intel_disable_planes(crtc);
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intel_disable_primary_hw_plane(dev_priv, plane, pipe);
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}
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/*
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* This implements the workaround described in the "notes" section of the mode
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* set sequence documentation. When going from no pipes or single pipe to
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@ -3836,7 +3829,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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/* If we change the relative order between pipe/planes enabling, we need
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* to change the workaround. */
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haswell_mode_set_planes_workaround(intel_crtc);
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haswell_crtc_enable_planes(crtc);
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ilk_crtc_enable_planes(crtc);
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}
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static void ironlake_pfit_disable(struct intel_crtc *crtc)
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@ -3861,26 +3854,16 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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u32 reg, temp;
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if (!intel_crtc->active)
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return;
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ilk_crtc_disable_planes(crtc);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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encoder->disable(encoder);
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intel_crtc_wait_for_pending_flips(crtc);
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drm_vblank_off(dev, pipe);
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if (dev_priv->fbc.plane == plane)
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intel_disable_fbc(dev);
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intel_crtc_update_cursor(crtc, false);
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intel_disable_planes(crtc);
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intel_disable_primary_hw_plane(dev_priv, plane, pipe);
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if (intel_crtc->config.has_pch_encoder)
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intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
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@ -3939,7 +3922,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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if (!intel_crtc->active)
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return;
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haswell_crtc_disable_planes(crtc);
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ilk_crtc_disable_planes(crtc);
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for_each_encoder_on_crtc(dev, crtc, encoder) {
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intel_opregion_notify_encoder(encoder, false);
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