dt: bindings: mtd: replace references to nand.txt with nand-controller.yaml
nand-controller.yaml replaced nand.txt however the references to it were
not updated. This change updates these references wherever it appears in
bindings documentation.
Fixes: 212e496935 ("dt-bindings: mtd: Add YAML schemas for the generic NAND options")
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
hifive-unleashed-5.2
Kamal Dasu
Rob Herring
parent
8d665693c2
commit
a5f2246fb9
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@ -24,7 +24,7 @@ Optional children nodes:
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Children nodes represent the available nand chips.
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Other properties:
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see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
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see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
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Example demonstrate on AXG SoC:
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@ -101,12 +101,12 @@ Required properties:
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number (e.g., 0, 1, 2, etc.)
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- #address-cells : see partition.txt
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- #size-cells : see partition.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : must be 512 or 1024. See nand.txt
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- nand-ecc-strength : see nand-controller.yaml
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- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
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Optional properties:
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- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
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chip-select. See nand.txt
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chip-select. See nand-controller.yaml
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- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
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expected for the ECC layout in use. This size, in
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addition to the strength and step-size,
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@ -22,16 +22,16 @@ Sub-nodes:
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select is connected.
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Optional properties:
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- nand-ecc-step-size: see nand.txt for details.
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- nand-ecc-step-size: see nand-controller.yaml for details.
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If present, the value must be
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512 for "altr,socfpga-denali-nand"
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1024 for "socionext,uniphier-denali-nand-v5a"
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1024 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-strength: see nand.txt for details. Valid values are:
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- nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
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8, 15 for "altr,socfpga-denali-nand"
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8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
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8, 16 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-maximize: see nand.txt for details
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- nand-ecc-maximize: see nand-controller.yaml for details
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The chip nodes may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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@ -30,9 +30,9 @@ Optional properties:
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command is asserted. Zero means one cycle, 255 means 256
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cycles.
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- bank: default NAND bank to use (0-3 are valid, 0 is the default).
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- nand-ecc-mode : see nand.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : see nand.txt
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- nand-ecc-mode : see nand-controller.yaml
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- nand-ecc-strength : see nand-controller.yaml
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- nand-ecc-step-size : see nand-controller.yaml
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Can support 1-bit HW ECC (default) or if stronger correction is required,
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software-based BCH.
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@ -8,7 +8,7 @@ explained in a separate documents - please refer to
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Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
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For NAND specific properties such as ECC modes or bus width, please refer to
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Documentation/devicetree/bindings/mtd/nand.txt
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Documentation/devicetree/bindings/mtd/nand-controller.yaml
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Required properties:
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@ -7,7 +7,7 @@ Required properties:
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NAND controller's registers. The second contains base
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physical address and size of NAND controller's buffer.
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- interrupts: Interrupt number for nfc.
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- nand-bus-width: See nand.txt.
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- nand-bus-width: See nand-controller.yaml.
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- nand-ecc-mode: Support none and hw ecc mode.
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- #address-cells: Partition address, should be set 1.
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- #size-cells: Partition size, should be set 1.
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@ -36,29 +36,29 @@ Children nodes represent the available NAND chips.
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Required properties:
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- reg: shall contain the native Chip Select ids (0-3).
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- nand-rb: see nand.txt (0-1).
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- nand-rb: see nand-controller.yaml (0-1).
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Optional properties:
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- marvell,nand-keep-config: orders the driver not to take the timings
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from the core and leaving them completely untouched. Bootloader
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timings will then be used.
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- label: MTD name.
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- nand-on-flash-bbt: see nand.txt.
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- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
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- nand-ecc-algo: see nand.txt. This property is essentially useful when
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- nand-on-flash-bbt: see nand-controller.yaml.
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- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
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- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
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not using hardware ECC. Howerver, it may be added when using hardware
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ECC for clarification but will be ignored by the driver because ECC
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mode is chosen depending on the page size and the strength required by
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the NAND chip. This value may be overwritten with nand-ecc-strength
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property.
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- nand-ecc-strength: see nand.txt.
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- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
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- nand-ecc-strength: see nand-controller.yaml.
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- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
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use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
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step size will shrink or grow in order to fit the required strength.
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Step sizes are not completely random for all and follow certain
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patterns described in AN-379, "Marvell SoC NFC ECC".
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See Documentation/devicetree/bindings/mtd/nand.txt for more details on
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See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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generic bindings.
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@ -4,9 +4,9 @@ Required properties:
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- compatible: "fsl,imxXX-nand"
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- reg: address range of the nfc block
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- interrupts: irq to be used
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- nand-bus-width: see nand.txt
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- nand-ecc-mode: see nand.txt
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- nand-on-flash-bbt: see nand.txt
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- nand-bus-width: see nand-controller.yaml
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- nand-ecc-mode: see nand-controller.yaml
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- nand-on-flash-bbt: see nand-controller.yaml
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Example:
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@ -26,14 +26,14 @@ Optional children node properties:
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"hw" is supported.
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- nand-ecc-algo: string, algorithm of NAND ECC.
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Supported values with "hw" ECC mode are: "rs", "bch".
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- nand-bus-width : See nand.txt
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- nand-on-flash-bbt: See nand.txt
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- nand-bus-width : See nand-controller.yaml
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- nand-on-flash-bbt: See nand-controller.yaml
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- nand-ecc-strength: integer representing the number of bits to correct
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per ECC step (always 512). Supported strength using HW ECC
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modes are:
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- RS: 4, 6, 8
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- BCH: 4, 8, 14, 16
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- nand-ecc-maximize: See nand.txt
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- nand-ecc-maximize: See nand-controller.yaml
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- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
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are chosen.
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- wp-gpios: GPIO specifier for the write protect pin.
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@ -1,6 +1,6 @@
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* Oxford Semiconductor OXNAS NAND Controller
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Please refer to nand.txt for generic information regarding MTD NAND bindings.
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Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
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Required properties:
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- compatible: "oxsemi,ox820-nand"
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@ -47,8 +47,8 @@ Required properties:
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- #size-cells: see partition.txt
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Optional properties:
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- nand-bus-width: see nand.txt
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- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
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- nand-bus-width: see nand-controller.yaml
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- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
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be used according to chip requirement and available
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OOB size.
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@ -6,7 +6,7 @@ Required properties:
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"samsung,s3c2412-nand"
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"samsung,s3c2440-nand"
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- reg : register's location and length.
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- #address-cells, #size-cells : see nand.txt
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- #address-cells, #size-cells : see nand-controller.yaml
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- clocks : phandle to the nand controller clock
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- clock-names : must contain "nand"
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@ -14,8 +14,8 @@ Optional child nodes:
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Child nodes representing the available nand chips.
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Optional child properties:
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- nand-ecc-mode : see nand.txt
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- nand-on-flash-bbt : see nand.txt
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- nand-ecc-mode : see nand-controller.yaml
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- nand-on-flash-bbt : see nand-controller.yaml
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Each child device node may optionally contain a 'partitions' sub-node,
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which further contains sub-nodes describing the flash partition mapping.
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@ -24,9 +24,9 @@ Required properties:
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- reg: describes the CS lines assigned to the NAND device.
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Optional properties:
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- nand-on-flash-bbt: see nand.txt
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- nand-ecc-strength: see nand.txt
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- nand-ecc-step-size: see nand.txt
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- nand-on-flash-bbt: see nand-controller.yaml
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- nand-ecc-strength: see nand-controller.yaml
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- nand-ecc-step-size: see nand-controller.yaml
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The following ECC strength and step size are currently supported:
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- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
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@ -11,7 +11,7 @@ Required properties:
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- #size-cells: <0>
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Children nodes represent the available NAND chips.
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See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
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See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
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Example:
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@ -25,14 +25,14 @@ only handle one NAND chip.
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Required properties:
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- compatible: Should be set to "fsl,vf610-nfc-cs".
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- nand-bus-width: see nand.txt
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- nand-ecc-mode: see nand.txt
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- nand-bus-width: see nand-controller.yaml
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- nand-ecc-mode: see nand-controller.yaml
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Required properties for hardware ECC:
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- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt)
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- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
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- nand-ecc-step-size: step size equals page size, currently only 2k pages are
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supported
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- nand-on-flash-bbt: see nand.txt
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- nand-on-flash-bbt: see nand-controller.yaml
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Example:
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