Use physical addresses at the interface level, letting drivers remap
them as appropriate. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Maciej W. Rozycki
Ralf Baechle
parent
7d7ee22121
commit
a5fc9c0bbe
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@ -227,11 +227,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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*/
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static inline void dec_kn02_be_init(void)
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{
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volatile u32 *csr = (void *)KN02_CSR_BASE;
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volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
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unsigned long flags;
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kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR);
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kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN);
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kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
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kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
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spin_lock_irqsave(&kn02_lock, flags);
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@ -250,11 +250,11 @@ static inline void dec_kn02_be_init(void)
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static inline void dec_kn03_be_init(void)
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{
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volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);
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volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
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volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
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volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
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kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
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kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
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kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
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kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
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/*
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* Set normal ECC detection and generation, enable ECC correction.
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@ -2,9 +2,9 @@
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* arch/mips/dec/int-handler.S
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*
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* Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
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* Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki
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* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
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*
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* Written by Ralf Baechle and Andreas Busse, modified for DECStation
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* Written by Ralf Baechle and Andreas Busse, modified for DECstation
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* support by Paul Antoine and Harald Koerfgen.
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*
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* completly rewritten:
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@ -14,11 +14,12 @@
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* by Maciej W. Rozycki.
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*/
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#include <linux/config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/dec/interrupts.h>
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#include <asm/dec/ioasic_addrs.h>
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@ -28,11 +29,14 @@
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#include <asm/dec/kn02xa.h>
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#include <asm/dec/kn03.h>
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#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
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#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
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#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
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.text
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.set noreorder
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/*
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* decstation_handle_int: Interrupt handler for DECStations
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* decstation_handle_int: Interrupt handler for DECstations
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*
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* We follow the model in the Indy interrupt code by David Miller, where he
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* says: a lot of complication here is taken away because:
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@ -48,7 +52,7 @@
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* 3) Linux only thinks in terms of all IRQs on or all IRQs
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* off, nothing in between like BSD spl() brain-damage.
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*
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* Furthermore, the IRQs on the DECStations look basically (barring
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* Furthermore, the IRQs on the DECstations look basically (barring
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* software IRQs which we don't use at all) like...
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*
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* DS2100/3100's, aka kn01, aka Pmax:
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@ -61,7 +65,7 @@
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* 3 Lance Ethernet
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* 4 DZ11 serial
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* 5 RTC
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* 6 Memory Controller
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* 6 Memory Controller & Video
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* 7 FPU
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*
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* DS5000/200, aka kn02, aka 3max:
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@ -51,7 +51,7 @@ DEFINE_SPINLOCK(kn01_lock);
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static inline void dec_kn01_be_ack(void)
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{
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volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
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unsigned long flags;
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spin_lock_irqsave(&kn01_lock, flags);
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@ -64,7 +64,8 @@ static inline void dec_kn01_be_ack(void)
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static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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{
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volatile u32 *kn01_erraddr = (void *)(KN01_SLOT_BASE + KN01_ERRADDR);
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volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
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KN01_ERRADDR);
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static const char excstr[] = "exception";
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static const char intstr[] = "interrupt";
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@ -152,7 +153,7 @@ int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
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irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
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int action;
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if (!(*csr & KN01_CSR_MEMERR))
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@ -178,7 +179,7 @@ irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
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void __init dec_kn01_be_init(void)
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{
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volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
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unsigned long flags;
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spin_lock_irqsave(&kn01_lock, flags);
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@ -37,7 +37,8 @@ static int kn02_irq_base;
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static inline void unmask_kn02_irq(unsigned int irq)
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{
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volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
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static inline void mask_kn02_irq(unsigned int irq)
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{
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volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
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*csr = cached_kn02_csr;
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@ -105,7 +107,8 @@ static struct hw_interrupt_type kn02_irq_type = {
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void __init init_kn02_irqs(int base)
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{
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volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE;
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
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KN02_CSR);
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unsigned long flags;
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int i;
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@ -20,6 +20,7 @@
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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@ -29,8 +30,8 @@
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static inline void dec_kn02xa_be_ack(void)
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{
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volatile u32 *mer = (void *)KN02XA_MER;
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volatile u32 *mem_intr = (void *)KN02XA_MEM_INTR;
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volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
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volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
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*mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
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*mem_intr = 0; /* Any write clears the bus IRQ. */
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@ -40,8 +41,8 @@ static inline void dec_kn02xa_be_ack(void)
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static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
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int invoker)
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{
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volatile u32 *kn02xa_mer = (void *)KN02XA_MER;
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volatile u32 *kn02xa_ear = (void *)KN02XA_EAR;
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volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
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volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
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static const char excstr[] = "exception";
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static const char intstr[] = "interrupt";
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@ -126,7 +127,7 @@ irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
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void __init dec_kn02xa_be_init(void)
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{
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volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
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volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
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/* For KN04 we need to make sure EE (?) is enabled in the MB. */
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if (current_cpu_data.cputype == CPU_R4000SC)
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@ -2,7 +2,7 @@
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* identify.c: machine identification code.
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*
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* Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
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* Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -12,6 +12,7 @@
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#include <linux/types.h>
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#include <asm/bootinfo.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/kn01.h>
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@ -21,6 +22,7 @@
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#include <asm/dec/kn03.h>
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#include <asm/dec/kn230.h>
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#include <asm/dec/prom.h>
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#include <asm/dec/system.h>
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#include "dectypes.h"
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@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
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static inline void prom_init_kn01(void)
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{
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dec_rtc_base = (void *)KN01_RTC_BASE;
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dec_kn_slot_base = KN01_SLOT_BASE;
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dec_kn_slot_size = KN01_SLOT_SIZE;
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dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
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}
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static inline void prom_init_kn230(void)
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{
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dec_rtc_base = (void *)KN01_RTC_BASE;
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dec_kn_slot_base = KN01_SLOT_BASE;
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dec_kn_slot_size = KN01_SLOT_SIZE;
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dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
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}
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static inline void prom_init_kn02(void)
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{
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dec_rtc_base = (void *)KN02_RTC_BASE;
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dec_kn_slot_base = KN02_SLOT_BASE;
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dec_kn_slot_size = KN02_SLOT_SIZE;
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dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
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}
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static inline void prom_init_kn02xa(void)
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{
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ioasic_base = (void *)KN02XA_IOASIC_BASE;
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dec_rtc_base = (void *)KN02XA_RTC_BASE;
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dec_kn_slot_base = KN02XA_SLOT_BASE;
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dec_kn_slot_size = IOASIC_SLOT_SIZE;
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ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
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dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
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}
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static inline void prom_init_kn03(void)
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{
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ioasic_base = (void *)KN03_IOASIC_BASE;
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dec_rtc_base = (void *)KN03_RTC_BASE;
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dec_kn_slot_base = KN03_SLOT_BASE;
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dec_kn_slot_size = IOASIC_SLOT_SIZE;
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ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
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dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
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}
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@ -39,6 +39,7 @@
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#include <asm/dec/kn02ca.h>
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#include <asm/dec/kn03.h>
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#include <asm/dec/kn230.h>
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#include <asm/dec/system.h>
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extern void dec_machine_restart(char *command);
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@ -48,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
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extern asmlinkage void decstation_handle_int(void);
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unsigned long dec_kn_slot_base, dec_kn_slot_size;
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EXPORT_SYMBOL(dec_kn_slot_base);
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EXPORT_SYMBOL(dec_kn_slot_size);
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spinlock_t ioasic_ssr_lock;
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volatile u32 *ioasic_base;
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unsigned long dec_kn_slot_size;
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EXPORT_SYMBOL(ioasic_base);
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/*
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* IRQ routing and priority tables. Priorites are set as follows:
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@ -78,6 +85,9 @@ unsigned long dec_kn_slot_size;
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int dec_interrupt[DEC_NR_INTS] = {
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[0 ... DEC_NR_INTS - 1] = -1
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};
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EXPORT_SYMBOL(dec_interrupt);
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int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
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{ { .i = ~0 }, { .p = dec_intr_unimplemented } },
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};
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@ -755,7 +765,3 @@ void __init arch_init_irq(void)
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if (dec_interrupt[DEC_IRQ_HALT] >= 0)
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setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
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}
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EXPORT_SYMBOL(ioasic_base);
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EXPORT_SYMBOL(dec_kn_slot_size);
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EXPORT_SYMBOL(dec_interrupt);
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@ -10,31 +10,29 @@
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* Copyright (c) Harald Koerfgen, 1998
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* Copyright (c) 2001, 2003, 2005 Maciej W. Rozycki
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*/
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/paccess.h>
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#include <asm/dec/machtype.h>
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#include <asm/dec/prom.h>
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#include <asm/dec/tcinfo.h>
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#include <asm/dec/tcmodule.h>
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#include <asm/dec/interrupts.h>
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#include <asm/paccess.h>
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#include <asm/ptrace.h>
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#define TC_DEBUG
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MODULE_LICENSE("GPL");
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slot_info tc_bus[MAX_SLOT];
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static int num_tcslots;
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static tcinfo *info;
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unsigned long system_base;
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/*
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* Interface to the world. Read comment in include/asm-mips/tc.h.
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*/
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@ -97,13 +95,16 @@ unsigned long get_tc_speed(void)
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static void __init tc_probe(unsigned long startaddr, unsigned long size,
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int slots)
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{
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unsigned long slotaddr;
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int i, slot, err;
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long offset;
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unsigned char pattern[4];
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unsigned char *module;
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u8 pattern[4];
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volatile u8 *module;
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for (slot = 0; slot < slots; slot++) {
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module = (char *)(startaddr + slot * size);
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slotaddr = startaddr + slot * size;
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module = ioremap_nocache(slotaddr, size);
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BUG_ON(!module);
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offset = OLDCARD;
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@ -112,8 +113,10 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
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err |= get_dbe(pattern[1], module + OLDCARD + TC_PATTERN1);
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err |= get_dbe(pattern[2], module + OLDCARD + TC_PATTERN2);
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err |= get_dbe(pattern[3], module + OLDCARD + TC_PATTERN3);
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if (err)
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if (err) {
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iounmap(module);
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continue;
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}
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if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
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pattern[2] != 0xaa || pattern[3] != 0xff) {
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@ -124,16 +127,20 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
|
|||
err |= get_dbe(pattern[1], module + TC_PATTERN1);
|
||||
err |= get_dbe(pattern[2], module + TC_PATTERN2);
|
||||
err |= get_dbe(pattern[3], module + TC_PATTERN3);
|
||||
if (err)
|
||||
if (err) {
|
||||
iounmap(module);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
if (pattern[0] != 0x55 || pattern[1] != 0x00 ||
|
||||
pattern[2] != 0xaa || pattern[3] != 0xff)
|
||||
pattern[2] != 0xaa || pattern[3] != 0xff) {
|
||||
iounmap(module);
|
||||
continue;
|
||||
}
|
||||
|
||||
tc_bus[slot].base_addr = (unsigned long)module;
|
||||
for(i = 0; i < 8; i++) {
|
||||
tc_bus[slot].base_addr = slotaddr;
|
||||
for (i = 0; i < 8; i++) {
|
||||
tc_bus[slot].firmware[i] =
|
||||
module[TC_FIRM_VER + offset + 4 * i];
|
||||
tc_bus[slot].vendor[i] =
|
||||
|
|
@ -171,6 +178,8 @@ static void __init tc_probe(unsigned long startaddr, unsigned long size,
|
|||
tc_bus[slot].interrupt = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
iounmap(module);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -196,8 +205,8 @@ static int __init tc_init(void)
|
|||
tc_bus[i].flags = FREE;
|
||||
}
|
||||
|
||||
info = (tcinfo *) rex_gettcinfo();
|
||||
slot0addr = (unsigned long)CKSEG1ADDR(rex_slot_address(0));
|
||||
info = rex_gettcinfo();
|
||||
slot0addr = CPHYSADDR((long)rex_slot_address(0));
|
||||
|
||||
switch (mips_machtype) {
|
||||
case MACH_DS5000_200:
|
||||
|
|
@ -216,35 +225,21 @@ static int __init tc_init(void)
|
|||
|
||||
tc_clock = 10000 / info->clk_period;
|
||||
|
||||
if (TURBOCHANNEL && info->slot_size && slot0addr) {
|
||||
printk("TURBOchannel rev. %1d at %2d.%1d MHz ", info->revision,
|
||||
tc_clock / 10, tc_clock % 10);
|
||||
printk("(with%s parity)\n", info->parity ? "" : "out");
|
||||
if (info->slot_size && slot0addr) {
|
||||
pr_info("TURBOchannel rev. %d at %d.%d MHz (with%s parity)\n",
|
||||
info->revision, tc_clock / 10, tc_clock % 10,
|
||||
info->parity ? "" : "out");
|
||||
|
||||
slot_size = info->slot_size << 20;
|
||||
|
||||
tc_probe(slot0addr, slot_size, num_tcslots);
|
||||
|
||||
/*
|
||||
* All TURBOchannel DECstations have the onboard devices
|
||||
* where the (num_tcslots + 0 or 1 on DS5k/xx) Option Module
|
||||
* would be.
|
||||
*/
|
||||
if(mips_machtype == MACH_DS5000_XX)
|
||||
i = 1;
|
||||
else
|
||||
i = 0;
|
||||
|
||||
system_base = slot0addr + slot_size * (num_tcslots + i);
|
||||
|
||||
#ifdef TC_DEBUG
|
||||
for (i = 0; i < num_tcslots; i++)
|
||||
if (tc_bus[i].base_addr) {
|
||||
printk(" slot %d: ", i);
|
||||
printk("%s %s %s\n", tc_bus[i].vendor,
|
||||
tc_bus[i].name, tc_bus[i].firmware);
|
||||
}
|
||||
#endif
|
||||
for (i = 0; i < num_tcslots; i++) {
|
||||
if (!tc_bus[i].base_addr)
|
||||
continue;
|
||||
pr_info(" slot %d: %s %s %s\n", i, tc_bus[i].vendor,
|
||||
tc_bus[i].name, tc_bus[i].firmware);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -258,4 +253,3 @@ EXPORT_SYMBOL(release_tc_card);
|
|||
EXPORT_SYMBOL(get_tc_base_addr);
|
||||
EXPORT_SYMBOL(get_tc_irq_nr);
|
||||
EXPORT_SYMBOL(get_tc_speed);
|
||||
EXPORT_SYMBOL(system_base);
|
||||
|
|
|
|||
|
|
@ -65,14 +65,14 @@
|
|||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/dec/serial.h>
|
||||
|
||||
#ifdef CONFIG_MACH_DECSTATION
|
||||
#include <asm/dec/interrupts.h>
|
||||
#include <asm/dec/machtype.h>
|
||||
#include <asm/dec/tc.h>
|
||||
#include <asm/dec/ioasic_addrs.h>
|
||||
#endif
|
||||
#include <asm/dec/machtype.h>
|
||||
#include <asm/dec/serial.h>
|
||||
#include <asm/dec/system.h>
|
||||
#include <asm/dec/tc.h>
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
#include <asm/kgdb.h>
|
||||
#endif
|
||||
|
|
@ -1616,30 +1616,22 @@ static void __init probe_sccs(void)
|
|||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* When serial console is activated, tc_init has not been called yet
|
||||
* and system_base is undefined. Unfortunately we have to hardcode
|
||||
* system_base for this case :-(. HK
|
||||
*/
|
||||
switch(mips_machtype) {
|
||||
#ifdef CONFIG_MACH_DECSTATION
|
||||
case MACH_DS5000_2X0:
|
||||
case MACH_DS5900:
|
||||
system_base = CKSEG1ADDR(0x1f800000);
|
||||
n_chips = 2;
|
||||
zs_parms = &ds_parms;
|
||||
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
|
||||
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
|
||||
break;
|
||||
case MACH_DS5000_1XX:
|
||||
system_base = CKSEG1ADDR(0x1c000000);
|
||||
n_chips = 2;
|
||||
zs_parms = &ds_parms;
|
||||
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
|
||||
zs_parms->irq1 = dec_interrupt[DEC_IRQ_SCC1];
|
||||
break;
|
||||
case MACH_DS5000_XX:
|
||||
system_base = CKSEG1ADDR(0x1c000000);
|
||||
n_chips = 1;
|
||||
zs_parms = &ds_parms;
|
||||
zs_parms->irq0 = dec_interrupt[DEC_IRQ_SCC0];
|
||||
|
|
@ -1661,10 +1653,10 @@ static void __init probe_sccs(void)
|
|||
* The sccs reside on the high byte of the 16 bit IOBUS
|
||||
*/
|
||||
zs_channels[n_channels].control =
|
||||
(volatile unsigned char *)system_base +
|
||||
(volatile void *)CKSEG1ADDR(dec_kn_slot_base +
|
||||
(0 == chip ? zs_parms->scc0 : zs_parms->scc1) +
|
||||
(0 == channel ? zs_parms->channel_a_offset :
|
||||
zs_parms->channel_b_offset);
|
||||
zs_parms->channel_b_offset));
|
||||
zs_channels[n_channels].data =
|
||||
zs_channels[n_channels].control + 4;
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,8 @@
|
|||
|
||||
|
||||
/*
|
||||
* Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
|
||||
* Offsets for I/O ASIC registers
|
||||
* (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
|
||||
*/
|
||||
/* all systems */
|
||||
#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
|
||||
|
|
|
|||
|
|
@ -13,9 +13,7 @@
|
|||
#ifndef __ASM_MIPS_DEC_KN01_H
|
||||
#define __ASM_MIPS_DEC_KN01_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#define KN01_SLOT_BASE CKSEG1ADDR(0x10000000)
|
||||
#define KN01_SLOT_BASE 0x10000000
|
||||
#define KN01_SLOT_SIZE 0x01000000
|
||||
|
||||
/*
|
||||
|
|
@ -40,18 +38,10 @@
|
|||
#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
|
||||
|
||||
|
||||
/*
|
||||
* Some port addresses...
|
||||
*/
|
||||
#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
|
||||
#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
|
||||
#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
|
||||
|
||||
|
||||
/*
|
||||
* Frame buffer memory address.
|
||||
*/
|
||||
#define KN01_VFB_MEM CKSEG1ADDR(0x0fc00000)
|
||||
#define KN01_VFB_MEM 0x0fc00000
|
||||
|
||||
/*
|
||||
* CPU interrupt bits.
|
||||
|
|
|
|||
|
|
@ -13,11 +13,7 @@
|
|||
#ifndef __ASM_MIPS_DEC_KN02_H
|
||||
#define __ASM_MIPS_DEC_KN02_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/dec/ecc.h>
|
||||
|
||||
|
||||
#define KN02_SLOT_BASE CKSEG1ADDR(0x1fc00000)
|
||||
#define KN02_SLOT_BASE 0x1fc00000
|
||||
#define KN02_SLOT_SIZE 0x00080000
|
||||
|
||||
/*
|
||||
|
|
@ -33,14 +29,6 @@
|
|||
#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
|
||||
|
||||
|
||||
/*
|
||||
* Some port addresses...
|
||||
*/
|
||||
#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
|
||||
#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
|
||||
#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
|
||||
|
||||
|
||||
/*
|
||||
* System Control & Status Register bits.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,31 +17,23 @@
|
|||
#ifndef __ASM_MIPS_DEC_KN02XA_H
|
||||
#define __ASM_MIPS_DEC_KN02XA_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/dec/ioasic_addrs.h>
|
||||
|
||||
#define KN02XA_SLOT_BASE CKSEG1ADDR(0x1c000000)
|
||||
|
||||
/*
|
||||
* Some port addresses...
|
||||
*/
|
||||
#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
|
||||
#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
|
||||
|
||||
#define KN02XA_SLOT_BASE 0x1c000000
|
||||
|
||||
/*
|
||||
* Memory control ASIC registers.
|
||||
*/
|
||||
#define KN02XA_MER CKSEG1ADDR(0x0c400000) /* memory error register */
|
||||
#define KN02XA_MSR CKSEG1ADDR(0x0c800000) /* memory size register */
|
||||
#define KN02XA_MER 0x0c400000 /* memory error register */
|
||||
#define KN02XA_MSR 0x0c800000 /* memory size register */
|
||||
|
||||
/*
|
||||
* CPU control ASIC registers.
|
||||
*/
|
||||
#define KN02XA_MEM_CONF CKSEG1ADDR(0x0e000000) /* write timeout config */
|
||||
#define KN02XA_EAR CKSEG1ADDR(0x0e000004) /* error address register */
|
||||
#define KN02XA_BOOT0 CKSEG1ADDR(0x0e000008) /* boot 0 register */
|
||||
#define KN02XA_MEM_INTR CKSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
|
||||
#define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
|
||||
#define KN02XA_EAR 0x0e000004 /* error address register */
|
||||
#define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
|
||||
#define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
|
||||
|
||||
/*
|
||||
* Memory Error Register bits, common definitions.
|
||||
|
|
|
|||
|
|
@ -10,24 +10,15 @@
|
|||
*
|
||||
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
|
||||
* are by courtesy of Chris Fraser.
|
||||
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
|
||||
* Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki
|
||||
*/
|
||||
#ifndef __ASM_MIPS_DEC_KN03_H
|
||||
#define __ASM_MIPS_DEC_KN03_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/dec/ecc.h>
|
||||
#include <asm/dec/ioasic_addrs.h>
|
||||
|
||||
#define KN03_SLOT_BASE CKSEG1ADDR(0x1f800000)
|
||||
|
||||
/*
|
||||
* Some port addresses...
|
||||
*/
|
||||
#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
|
||||
#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
|
||||
#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
|
||||
|
||||
#define KN03_SLOT_BASE 0x1f800000
|
||||
|
||||
/*
|
||||
* CPU interrupt bits.
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
#ifndef __ASM_MIPS_DEC_KN05_H
|
||||
#define __ASM_MIPS_DEC_KN05_H
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/dec/ioasic_addrs.h>
|
||||
|
||||
/*
|
||||
|
|
@ -30,7 +29,7 @@
|
|||
* passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
|
||||
* Others are handled locally. "Low" slots are always passed.
|
||||
*/
|
||||
#define KN4K_SLOT_BASE KSEG1ADDR(0x1fc00000)
|
||||
#define KN4K_SLOT_BASE 0x1fc00000
|
||||
|
||||
#define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
|
||||
#define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* include/asm-mips/dec/system.h
|
||||
*
|
||||
* Generic DECstation/DECsystem bits.
|
||||
*
|
||||
* Copyright (C) 2005 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#ifndef __ASM_DEC_SYSTEM_H
|
||||
#define __ASM_DEC_SYSTEM_H
|
||||
|
||||
extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
|
||||
|
||||
#endif /* __ASM_DEC_SYSTEM_H */
|
||||
|
|
@ -7,10 +7,8 @@
|
|||
*
|
||||
* Copyright (c) 1998 Harald Koerfgen
|
||||
*/
|
||||
#ifndef ASM_TC_H
|
||||
#define ASM_TC_H
|
||||
|
||||
extern unsigned long system_base;
|
||||
#ifndef __ASM_DEC_TC_H
|
||||
#define __ASM_DEC_TC_H
|
||||
|
||||
/*
|
||||
* Search for a TURBOchannel Option Module
|
||||
|
|
@ -36,8 +34,8 @@ extern unsigned long get_tc_base_addr(int);
|
|||
*/
|
||||
extern unsigned long get_tc_irq_nr(int);
|
||||
/*
|
||||
* Return TURBOchannel clock frequency in hz
|
||||
* Return TURBOchannel clock frequency in Hz
|
||||
*/
|
||||
extern unsigned long get_tc_speed(void);
|
||||
|
||||
#endif
|
||||
#endif /* __ASM_DEC_TC_H */
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 1998, 2001 by Ralf Baechle
|
||||
* Copyright (C) 1998 by Harald Koerfgen
|
||||
* Copyright (C) 2002 Maciej W. Rozycki
|
||||
* Copyright (C) 2002, 2005 Maciej W. Rozycki
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
|
|
@ -14,23 +14,18 @@
|
|||
#define __ASM_MIPS_DEC_RTC_DEC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/dec/system.h>
|
||||
|
||||
extern volatile u8 *dec_rtc_base;
|
||||
extern unsigned long dec_kn_slot_size;
|
||||
|
||||
#define RTC_PORT(x) CPHYSADDR(dec_rtc_base)
|
||||
#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
|
||||
#define RTC_IO_EXTENT dec_kn_slot_size
|
||||
#define RTC_IOMAPPED 0
|
||||
#undef RTC_IRQ
|
||||
|
||||
#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
|
||||
|
||||
#include <linux/mc146818rtc.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
static inline unsigned char CMOS_READ(unsigned long addr)
|
||||
{
|
||||
return dec_rtc_base[addr * 4];
|
||||
|
|
|
|||
Loading…
Reference in New Issue