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drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display. 

For virtual display feature, if user set the option "amdgpu.virtual_display=1"
when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip
blocks. And when enable virtual display, the amdgpu_dal need to be set to zero.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Emily Deng 2016-08-08 11:37:50 +08:00 committed by Alex Deucher
parent e443059d0f
commit a6be757051
3 changed files with 113 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -1185,6 +1185,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
{
int i, r;
DRM_INFO("virtual display enabled:%d\n", amdgpu_virtual_display);
switch (adev->asic_type) {
case CHIP_TOPAZ:
case CHIP_TONGA:

77
drivers/gpu/drm/amd/amdgpu/cik.c
View File

@ -2323,30 +2323,59 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
int cik_set_ip_blocks(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_BONAIRE:
adev->ip_blocks = bonaire_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
break;
case CHIP_HAWAII:
adev->ip_blocks = hawaii_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
break;
case CHIP_KAVERI:
adev->ip_blocks = kaveri_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
break;
case CHIP_KABINI:
adev->ip_blocks = kabini_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
break;
case CHIP_MULLINS:
adev->ip_blocks = mullins_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
if (amdgpu_virtual_display) {
adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
switch (adev->asic_type) {
case CHIP_BONAIRE:
adev->ip_blocks = bonaire_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
break;
case CHIP_HAWAII:
adev->ip_blocks = hawaii_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
break;
case CHIP_KAVERI:
adev->ip_blocks = kaveri_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
break;
case CHIP_KABINI:
adev->ip_blocks = kabini_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
break;
case CHIP_MULLINS:
adev->ip_blocks = mullins_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
}
} else {
switch (adev->asic_type) {
case CHIP_BONAIRE:
adev->ip_blocks = bonaire_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
break;
case CHIP_HAWAII:
adev->ip_blocks = hawaii_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
break;
case CHIP_KAVERI:
adev->ip_blocks = kaveri_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
break;
case CHIP_KABINI:
adev->ip_blocks = kabini_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
break;
case CHIP_MULLINS:
adev->ip_blocks = mullins_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
}
}
return 0;

84
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -1387,32 +1387,64 @@ static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
int vi_set_ip_blocks(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_TOPAZ:
adev->ip_blocks = topaz_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
break;
case CHIP_FIJI:
adev->ip_blocks = fiji_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
break;
case CHIP_TONGA:
adev->ip_blocks = tonga_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
adev->ip_blocks = polaris11_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
break;
case CHIP_CARRIZO:
case CHIP_STONEY:
adev->ip_blocks = cz_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
if (amdgpu_virtual_display) {
adev->mode_info.vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
switch (adev->asic_type) {
case CHIP_TOPAZ:
adev->ip_blocks = topaz_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
break;
case CHIP_FIJI:
adev->ip_blocks = fiji_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
break;
case CHIP_TONGA:
adev->ip_blocks = tonga_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
adev->ip_blocks = polaris11_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
break;
case CHIP_CARRIZO:
case CHIP_STONEY:
adev->ip_blocks = cz_ip_blocks_vd;
adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
}
} else {
switch (adev->asic_type) {
case CHIP_TOPAZ:
adev->ip_blocks = topaz_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
break;
case CHIP_FIJI:
adev->ip_blocks = fiji_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
break;
case CHIP_TONGA:
adev->ip_blocks = tonga_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
adev->ip_blocks = polaris11_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
break;
case CHIP_CARRIZO:
case CHIP_STONEY:
adev->ip_blocks = cz_ip_blocks;
adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
break;
default:
/* FIXME: not supported yet */
return -EINVAL;
}
}
return 0;