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clk: imx7d: set PLL_SYS_MAIN as parent clock of epdc pixel clock 

set PLL_SYS_MAIN as EPDC pixel_clock's parent clock to get desired clock

Signed-off-by: Robby Cai <robby.cai@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Robby Cai 2019-08-21 08:51:16 -04:00 committed by Dong Aisheng
parent 85812d2eb7
commit a6f73ca594
1 changed files with 3 additions and 0 deletions
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3
drivers/clk/imx/clk-imx7d.c
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@ -904,6 +904,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
/* set parent of EPDC pixel clock */
clk_set_parent(hws[IMX7D_EPDC_PIXEL_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_MAIN_CLK]->clk);
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
int index = uart_clk_ids[i];