redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration 

USB0 48MHz PHY clock registration fails on DA830 because the
da8xx-cfgchip clock driver cannot get a reference to USB0
LPSC clock.

The USB0 LPSC needs to be enabled during PHY clock enable. Setup
the clock lookup correctly to fix this.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
hifive-unleashed-5.1
Sekhar Nori 2018-05-07 17:04:57 +05:30 committed by Stephen Boyd
parent 60cc43fc88
commit a714dceb72
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/clk/davinci/psc-da830.c
View File

@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = {
.psc_init = &da830_psc0_init,
};
LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx",
LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
NULL, "musb-da8xx",
NULL, "cppi41-dmaengine");
LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
/* REVISIT: gpio-davinci.c should be modified to drop con_id */