drm/i915: Use dev_priv in public intel_fifo_underrun.c functions
It's the new rule! Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>hifive-unleashed-5.1
Daniel Vetter
parent
47339cd9ff
commit
a72e4c9f9a
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@ -1750,7 +1750,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
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* handle.
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*/
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mask = 0;
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if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
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if (__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe))
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mask |= PIPE_FIFO_UNDERRUN_STATUS;
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switch (pipe) {
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@ -1797,7 +1797,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
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false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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@ -1965,12 +1966,14 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
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DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
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if (pch_iir & SDE_TRANSA_FIFO_UNDER)
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if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
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if (intel_set_pch_fifo_underrun_reporting(dev_priv,
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TRANSCODER_A,
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false))
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DRM_ERROR("PCH transcoder A FIFO underrun\n");
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if (pch_iir & SDE_TRANSB_FIFO_UNDER)
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if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
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if (intel_set_pch_fifo_underrun_reporting(dev_priv,
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TRANSCODER_B,
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false))
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DRM_ERROR("PCH transcoder B FIFO underrun\n");
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}
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@ -1986,7 +1989,7 @@ static void ivb_err_int_handler(struct drm_device *dev)
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for_each_pipe(dev_priv, pipe) {
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if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
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if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
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if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
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false))
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DRM_ERROR("Pipe %c FIFO underrun\n",
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pipe_name(pipe));
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@ -2012,17 +2015,17 @@ static void cpt_serr_int_handler(struct drm_device *dev)
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DRM_ERROR("PCH poison interrupt\n");
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if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
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if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
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if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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false))
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DRM_ERROR("PCH transcoder A FIFO underrun\n");
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if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
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if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
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if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,
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false))
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DRM_ERROR("PCH transcoder B FIFO underrun\n");
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if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
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if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
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if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,
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false))
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DRM_ERROR("PCH transcoder C FIFO underrun\n");
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@ -2090,7 +2093,9 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
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intel_check_page_flip(dev, pipe);
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if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
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if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
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pipe,
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false))
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DRM_ERROR("Pipe %c FIFO underrun\n",
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pipe_name(pipe));
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@ -2312,7 +2317,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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hsw_pipe_crc_irq_handler(dev, pipe);
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if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
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if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
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if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
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pipe,
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false))
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DRM_ERROR("Pipe %c FIFO underrun\n",
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pipe_name(pipe));
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@ -3834,7 +3840,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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intel_set_cpu_fifo_underrun_reporting(dev_priv,
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pipe, false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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@ -4028,7 +4035,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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intel_set_cpu_fifo_underrun_reporting(dev_priv,
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pipe, false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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@ -4256,7 +4264,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
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i9xx_pipe_crc_irq_handler(dev, pipe);
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
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intel_set_cpu_fifo_underrun_reporting(dev_priv,
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pipe, false))
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DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
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}
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@ -4163,8 +4163,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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intel_crtc->active = true;
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_enable)
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@ -4278,13 +4278,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_crtc->active = true;
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_enable)
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encoder->pre_enable(encoder);
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if (intel_crtc->config.has_pch_encoder) {
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intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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true);
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dev_priv->display.fdi_link_train(crtc);
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}
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@ -4360,7 +4361,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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encoder->disable(encoder);
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if (intel_crtc->config.has_pch_encoder)
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intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
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intel_disable_pipe(intel_crtc);
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@ -4374,7 +4375,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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ironlake_fdi_disable(crtc);
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ironlake_disable_pch_transcoder(dev_priv, pipe);
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intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
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if (HAS_PCH_CPT(dev)) {
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/* disable TRANS_DP_CTL */
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@ -4427,7 +4428,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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}
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if (intel_crtc->config.has_pch_encoder)
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intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
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intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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false);
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intel_disable_pipe(intel_crtc);
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if (intel_crtc->config.dp_encoder_is_mst)
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@ -4441,7 +4443,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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if (intel_crtc->config.has_pch_encoder) {
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lpt_disable_pch_transcoder(dev_priv);
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intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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true);
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intel_ddi_fdi_disable(crtc);
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}
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@ -4818,6 +4821,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
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static void valleyview_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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@ -4846,7 +4850,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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intel_crtc->active = true;
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_pll_enable)
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@ -4879,7 +4883,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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intel_crtc_enable_planes(crtc);
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/* Underruns don't raise interrupts, so check manually. */
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i9xx_check_fifo_underruns(dev);
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i9xx_check_fifo_underruns(dev_priv);
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}
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static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
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@ -4894,6 +4898,7 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
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static void i9xx_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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@ -4915,7 +4920,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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intel_crtc->active = true;
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if (!IS_GEN2(dev))
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_enable)
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@ -4946,10 +4951,10 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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* but leave the pipe running.
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*/
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if (IS_GEN2(dev))
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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/* Underruns don't raise interrupts, so check manually. */
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i9xx_check_fifo_underruns(dev);
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i9xx_check_fifo_underruns(dev_priv);
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}
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static void i9xx_pfit_disable(struct intel_crtc *crtc)
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@ -4985,7 +4990,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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* but leave the pipe running.
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*/
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if (IS_GEN2(dev))
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
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/*
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* Vblank time updates from the shadow to live plane control register
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@ -5031,7 +5036,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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}
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if (!IS_GEN2(dev))
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intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
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intel_crtc->active = false;
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intel_update_watermarks(crtc);
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@ -756,13 +756,13 @@ static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
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}
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/* intel_fifo_underrun.c */
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool enable);
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bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
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bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum transcoder pch_transcoder,
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bool enable);
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void i9xx_check_fifo_underruns(struct drm_device *dev);
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bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
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void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
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bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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/* i915_irq.c */
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@ -64,14 +64,13 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
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return true;
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}
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void i9xx_check_fifo_underruns(struct drm_device *dev)
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void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc;
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spin_lock_irq(&dev_priv->irq_lock);
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for_each_intel_crtc(dev, crtc) {
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for_each_intel_crtc(dev_priv->dev, crtc) {
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u32 reg = PIPESTAT(crtc->pipe);
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u32 pipestat;
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@ -239,24 +238,23 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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return old;
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}
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
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bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum pipe pipe, bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long flags;
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bool ret;
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
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ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe,
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enable);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return ret;
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}
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bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
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bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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@ -277,11 +275,10 @@ bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
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*
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* Returns the previous state of underrun reporting.
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*/
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bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
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bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
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enum transcoder pch_transcoder,
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bool enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long flags;
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@ -301,10 +298,12 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
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old = !intel_crtc->pch_fifo_underrun_disabled;
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intel_crtc->pch_fifo_underrun_disabled = !enable;
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if (HAS_PCH_IBX(dev))
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ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
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if (HAS_PCH_IBX(dev_priv->dev))
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ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,
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enable);
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else
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cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
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cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,
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enable, old);
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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return old;
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