ASoC: Intel: Skylake: Add SKL DSP initialization
This adds the dsp and ipc initialization for the Skylake platform. It also requests firmware and uses code loader dma to load it. Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com> Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Subhransu S. Prusty
Mark Brown
parent
6cb0033380
commit
a750ba5f5a
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@ -3,6 +3,7 @@ snd-soc-skl-objs := skl.o skl-pcm.o
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obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE) += snd-soc-skl.o
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# Skylake IPC Support
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snd-soc-skl-ipc-objs := skl-sst-ipc.o skl-sst-dsp.o skl-sst-cldma.o
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snd-soc-skl-ipc-objs := skl-sst-ipc.o skl-sst-dsp.o skl-sst-cldma.o \
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skl-sst.o
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obj-$(CONFIG_SND_SOC_INTEL_SKYLAKE) += snd-soc-skl-ipc.o
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@ -16,10 +16,12 @@
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#ifndef __SKL_SST_DSP_H__
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#define __SKL_SST_DSP_H__
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#include <linux/interrupt.h>
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#include <sound/memalloc.h>
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#include "skl-sst-cldma.h"
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struct sst_dsp;
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struct skl_sst;
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struct sst_dsp_device;
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/* Intel HD Audio General DSP Registers */
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@ -62,6 +64,11 @@ struct sst_dsp_device;
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#define SKL_ADSP_W1_SZ 0x1000
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#define SKL_FW_STS_MASK 0xf
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#define SKL_FW_INIT 0x1
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#define SKL_FW_RFW_START 0xf
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#define SKL_ADSPIC_IPC 1
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#define SKL_ADSPIS_IPC 1
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@ -106,6 +113,7 @@ struct skl_dsp_fw_ops {
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int (*parse_fw)(struct sst_dsp *ctx);
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int (*set_state_D0)(struct sst_dsp *ctx);
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int (*set_state_D3)(struct sst_dsp *ctx);
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unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
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};
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struct skl_dsp_loader_ops {
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@ -130,5 +138,8 @@ int skl_dsp_sleep(struct sst_dsp *ctx);
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void skl_dsp_free(struct sst_dsp *dsp);
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int skl_dsp_boot(struct sst_dsp *ctx);
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int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
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struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp);
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void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
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#endif /*__SKL_SST_DSP_H__*/
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@ -496,6 +496,8 @@ void skl_ipc_free(struct sst_generic_ipc *ipc)
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/* Disable IPC BUSY interrupt */
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sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
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SKL_ADSP_REG_HIPCCTL_BUSY, 0);
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sst_ipc_fini(ipc);
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}
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int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc,
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280
sound/soc/intel/skylake/skl-sst.c
Normal file
280
sound/soc/intel/skylake/skl-sst.c
Normal file
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@ -0,0 +1,280 @@
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/*
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* skl-sst.c - HDA DSP library functions for SKL platform
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*
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* Copyright (C) 2014-15, Intel Corporation.
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* Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
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* Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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#include "../common/sst-ipc.h"
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#include "skl-sst-ipc.h"
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#define SKL_BASEFW_TIMEOUT 300
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#define SKL_INIT_TIMEOUT 1000
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/* Intel HD Audio SRAM Window 0*/
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#define SKL_ADSP_SRAM0_BASE 0x8000
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/* Firmware status window */
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#define SKL_ADSP_FW_STATUS SKL_ADSP_SRAM0_BASE
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#define SKL_ADSP_ERROR_CODE (SKL_ADSP_FW_STATUS + 0x4)
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#define SKL_INSTANCE_ID 0
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#define SKL_BASE_FW_MODULE_ID 0
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static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
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{
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u32 cur_sts;
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cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
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return (cur_sts == status);
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}
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static int skl_transfer_firmware(struct sst_dsp *ctx,
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const void *basefw, u32 base_fw_size)
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{
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int ret = 0;
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ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size);
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if (ret < 0)
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return ret;
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ret = sst_dsp_register_poll(ctx,
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SKL_ADSP_FW_STATUS,
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SKL_FW_STS_MASK,
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SKL_FW_RFW_START,
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SKL_BASEFW_TIMEOUT,
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"Firmware boot");
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ctx->cl_dev.ops.cl_stop_dma(ctx);
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return ret;
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}
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static int skl_load_base_firmware(struct sst_dsp *ctx)
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{
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int ret = 0, i;
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const struct firmware *fw = NULL;
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struct skl_sst *skl = ctx->thread_context;
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u32 reg;
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ret = request_firmware(&fw, "dsp_fw_release.bin", ctx->dev);
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if (ret < 0) {
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dev_err(ctx->dev, "Request firmware failed %d\n", ret);
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skl_dsp_disable_core(ctx);
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return -EIO;
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}
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/* enable Interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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/* check ROM Status */
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for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
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if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
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dev_dbg(ctx->dev,
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"ROM loaded, we can continue with FW loading\n");
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break;
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}
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mdelay(1);
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}
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if (!i) {
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reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
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dev_err(ctx->dev,
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"Timeout waiting for ROM init done, reg:0x%x\n", reg);
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ret = -EIO;
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goto skl_load_base_firmware_failed;
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}
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ret = skl_transfer_firmware(ctx, fw->data, fw->size);
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if (ret < 0) {
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dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
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goto skl_load_base_firmware_failed;
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} else {
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ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
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ret = -EIO;
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goto skl_load_base_firmware_failed;
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}
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dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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}
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release_firmware(fw);
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return 0;
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skl_load_base_firmware_failed:
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skl_dsp_disable_core(ctx);
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release_firmware(fw);
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return ret;
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}
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static int skl_set_dsp_D0(struct sst_dsp *ctx)
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{
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int ret;
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ret = skl_load_base_firmware(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "unable to load firmware\n");
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return ret;
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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return ret;
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}
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static int skl_set_dsp_D3(struct sst_dsp *ctx)
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{
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int ret;
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struct skl_ipc_dxstate_info dx;
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struct skl_sst *skl = ctx->thread_context;
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dev_dbg(ctx->dev, "In %s:\n", __func__);
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mutex_lock(&ctx->mutex);
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if (!is_skl_dsp_running(ctx)) {
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mutex_unlock(&ctx->mutex);
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return 0;
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}
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mutex_unlock(&ctx->mutex);
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dx.core_mask = SKL_DSP_CORE0_MASK;
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dx.dx_mask = SKL_IPC_D3_MASK;
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ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set DSP to D3 state\n");
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return ret;
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}
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ret = skl_dsp_disable_core(ctx);
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if (ret < 0) {
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dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret);
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ret = -EIO;
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
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return ret;
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}
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static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
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}
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static struct skl_dsp_fw_ops skl_fw_ops = {
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.set_state_D0 = skl_set_dsp_D0,
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.set_state_D3 = skl_set_dsp_D3,
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.load_fw = skl_load_base_firmware,
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.get_fw_errcode = skl_get_errorcode,
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};
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static struct sst_ops skl_ops = {
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.irq_handler = skl_dsp_sst_interrupt,
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.write = sst_shim32_write,
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.read = sst_shim32_read,
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.ram_read = sst_memcpy_fromio_32,
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.ram_write = sst_memcpy_toio_32,
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.free = skl_dsp_free,
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};
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static struct sst_dsp_device skl_dev = {
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.thread = skl_dsp_irq_thread_handler,
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.ops = &skl_ops,
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};
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int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
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struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp)
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{
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struct skl_sst *skl;
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struct sst_dsp *sst;
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int ret;
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skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
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if (skl == NULL)
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return -ENOMEM;
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skl->dev = dev;
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skl_dev.thread_context = skl;
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skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
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if (!skl->dsp) {
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dev_err(skl->dev, "%s: no device\n", __func__);
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return -ENODEV;
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}
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sst = skl->dsp;
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sst->addr.lpe = mmio_base;
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sst->addr.shim = mmio_base;
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sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
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SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
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sst->dsp_ops = dsp_ops;
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sst->fw_ops = skl_fw_ops;
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ret = skl_ipc_init(dev, skl);
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if (ret)
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return ret;
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skl->boot_complete = false;
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init_waitqueue_head(&skl->boot_wait);
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ret = skl_dsp_boot(sst);
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if (ret < 0) {
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dev_err(skl->dev, "Boot dsp core failed ret: %d", ret);
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goto free_ipc;
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}
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ret = skl_cldma_prepare(sst);
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if (ret < 0) {
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dev_err(dev, "CL dma prepare failed : %d", ret);
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goto free_ipc;
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}
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ret = sst->fw_ops.load_fw(sst);
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if (ret < 0) {
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dev_err(dev, "Load base fw failed : %d", ret);
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return ret;
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}
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if (dsp)
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*dsp = skl;
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return 0;
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free_ipc:
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skl_ipc_free(&skl->ipc);
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return ret;
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}
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EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
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void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
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{
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skl_ipc_free(&ctx->ipc);
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ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
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ctx->dsp->ops->free(ctx->dsp);
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}
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EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel Skylake IPC driver");
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