drm/i915: split out pll divider code
This cleans up the mode set path a little further, making it easier to extend for future platforms. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: shut up stupid gcc warning about potential use of un-initlized fp2] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5024,6 +5024,40 @@ static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
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}
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}
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static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
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intel_clock_t *clock,
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 fp, fp2 = 0;
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if (IS_PINEVIEW(dev)) {
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fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
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if (reduced_clock)
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fp2 = (1 << reduced_clock->n) << 16 |
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reduced_clock->m1 << 8 | reduced_clock->m2;
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} else {
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fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
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if (reduced_clock)
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fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
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reduced_clock->m2;
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}
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I915_WRITE(FP0(pipe), fp);
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intel_crtc->lowfreq_avail = false;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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reduced_clock && i915_powersave) {
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I915_WRITE(FP1(pipe), fp2);
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intel_crtc->lowfreq_avail = true;
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} else {
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I915_WRITE(FP1(pipe), fp);
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}
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}
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -5037,7 +5071,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
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u32 dpll, dspcntr, pipeconf;
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bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
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bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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@ -5113,17 +5147,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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if (is_sdvo && is_tv)
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i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
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if (IS_PINEVIEW(dev)) {
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fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = (1 << reduced_clock.n) << 16 |
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reduced_clock.m1 << 8 | reduced_clock.m2;
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} else {
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fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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if (has_reduced_clock)
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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}
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i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
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&reduced_clock : NULL);
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dpll = DPLL_VGA_MODE_DIS;
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@ -5233,7 +5258,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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I915_WRITE(FP0(pipe), fp);
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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@ -5320,17 +5344,11 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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I915_WRITE(DPLL(pipe), dpll);
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}
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intel_crtc->lowfreq_avail = false;
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if (is_lvds && has_reduced_clock && i915_powersave) {
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I915_WRITE(FP1(pipe), fp2);
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intel_crtc->lowfreq_avail = true;
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if (HAS_PIPE_CXSR(dev)) {
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if (HAS_PIPE_CXSR(dev)) {
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if (intel_crtc->lowfreq_avail) {
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DRM_DEBUG_KMS("enabling CxSR downclocking\n");
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pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
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}
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} else {
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I915_WRITE(FP1(pipe), fp);
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if (HAS_PIPE_CXSR(dev)) {
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} else {
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DRM_DEBUG_KMS("disabling CxSR downclocking\n");
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pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
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}
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