mtd: onenand: omap2: Configure driver from DT
Move away from platform data configuration and use pure DT approach. Use generic probe function to deal with OneNAND node and remove now useless gpmc_probe_onenand_child function. Import sync mode timing calculation function from mach-omap2/gpmc-onenand.c Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>hifive-unleashed-5.1
Ladislav Michl
Boris Brezillon
parent
bdaca9345d
commit
a758f50f10
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@ -32,7 +32,6 @@
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#include <linux/pm_runtime.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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#include <linux/platform_data/mtd-onenand-omap2.h>
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#include <asm/mach-types.h>
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@ -1138,6 +1137,112 @@ struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
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}
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EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
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static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
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struct gpmc_settings *s,
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int freq, int latency)
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{
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struct gpmc_device_timings dev_t;
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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switch (freq) {
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case 104:
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min_gpmc_clk_period = 9600; /* 104 MHz */
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t_ces = 3;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 3;
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t_aavdh = 6;
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t_rdyo = 6;
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break;
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case 83:
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min_gpmc_clk_period = 12000; /* 83 MHz */
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 9;
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break;
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case 66:
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min_gpmc_clk_period = 15000; /* 66 MHz */
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 11;
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break;
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default:
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min_gpmc_clk_period = 18500; /* 54 MHz */
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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break;
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}
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/* Set synchronous read timings */
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memset(&dev_t, 0, sizeof(dev_t));
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if (!s->sync_write) {
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dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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dev_t.t_aavdh = t_aavdh * 1000;
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}
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dev_t.ce_xdelay = true;
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dev_t.avd_xdelay = true;
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dev_t.oe_xdelay = true;
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dev_t.we_xdelay = true;
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dev_t.clk = min_gpmc_clk_period;
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dev_t.t_bacc = dev_t.clk;
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dev_t.t_ces = t_ces * 1000;
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dev_t.t_avds = t_avds * 1000;
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dev_t.t_avdh = t_avdh * 1000;
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dev_t.t_ach = t_ach * 1000;
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dev_t.cyc_iaa = (latency + 1);
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.cyc_aavdh_oe = 1;
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dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
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gpmc_calc_timings(t, s, &dev_t);
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}
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int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
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int latency,
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struct gpmc_onenand_info *info)
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{
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int ret;
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struct gpmc_timings gpmc_t;
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struct gpmc_settings gpmc_s;
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gpmc_read_settings_dt(dev->of_node, &gpmc_s);
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info->sync_read = gpmc_s.sync_read;
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info->sync_write = gpmc_s.sync_write;
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info->burst_len = gpmc_s.burst_len;
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if (!gpmc_s.sync_read && !gpmc_s.sync_write)
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return 0;
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gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
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ret = gpmc_cs_program_settings(cs, &gpmc_s);
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if (ret < 0)
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return ret;
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return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
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}
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EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
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int gpmc_get_client_irq(unsigned irq_config)
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{
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if (!gpmc_irq_domain) {
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@ -1916,41 +2021,6 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
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of_property_read_bool(np, "gpmc,time-para-granularity");
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}
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#if IS_ENABLED(CONFIG_MTD_ONENAND)
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static int gpmc_probe_onenand_child(struct platform_device *pdev,
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struct device_node *child)
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{
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u32 val;
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struct omap_onenand_platform_data *gpmc_onenand_data;
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if (of_property_read_u32(child, "reg", &val) < 0) {
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dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
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child);
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return -ENODEV;
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}
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gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
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GFP_KERNEL);
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if (!gpmc_onenand_data)
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return -ENOMEM;
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gpmc_onenand_data->cs = val;
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gpmc_onenand_data->of_node = child;
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gpmc_onenand_data->dma_channel = -1;
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if (!of_property_read_u32(child, "dma-channel", &val))
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gpmc_onenand_data->dma_channel = val;
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return gpmc_onenand_init(gpmc_onenand_data);
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}
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#else
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static int gpmc_probe_onenand_child(struct platform_device *pdev,
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struct device_node *child)
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{
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return 0;
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}
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#endif
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/**
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* gpmc_probe_generic_child - configures the gpmc for a child device
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* @pdev: pointer to gpmc platform device
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@ -2053,6 +2123,16 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
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}
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}
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if (of_node_cmp(child->name, "onenand") == 0) {
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/* Warn about older DT blobs with no compatible property */
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if (!of_property_read_bool(child, "compatible")) {
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dev_warn(&pdev->dev,
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"Incompatible OneNAND node: missing compatible");
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ret = -EINVAL;
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goto err;
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}
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}
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if (of_device_is_compatible(child, "ti,omap2-nand")) {
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/* NAND specific setup */
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val = 8;
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@ -2189,11 +2269,7 @@ static void gpmc_probe_dt_children(struct platform_device *pdev)
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if (!child->name)
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continue;
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if (of_node_cmp(child->name, "onenand") == 0)
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ret = gpmc_probe_onenand_child(pdev, child);
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else
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ret = gpmc_probe_generic_child(pdev, child);
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ret = gpmc_probe_generic_child(pdev, child);
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if (ret) {
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dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
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child->name, ret);
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@ -25,9 +25,11 @@ config MTD_ONENAND_GENERIC
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config MTD_ONENAND_OMAP2
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tristate "OneNAND on OMAP2/OMAP3 support"
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depends on ARCH_OMAP2 || ARCH_OMAP3
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depends on OF || COMPILE_TEST
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help
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Support for a OneNAND flash device connected to an OMAP2/OMAP3 CPU
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Support for a OneNAND flash device connected to an OMAP2/OMAP3 SoC
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via the GPMC memory controller.
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Enable dmaengine and gpiolib for better performance.
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config MTD_ONENAND_SAMSUNG
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tristate "OneNAND on Samsung SOC controller support"
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@ -28,6 +28,8 @@
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of_device.h>
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#include <linux/omap-gpmc.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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@ -35,10 +37,9 @@
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#include <linux/dmaengine.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/gpio/consumer.h>
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#include <asm/mach/flash.h>
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#include <linux/platform_data/mtd-onenand-omap2.h>
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#define DRIVER_NAME "omap2-onenand"
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@ -48,15 +49,12 @@ struct omap2_onenand {
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struct platform_device *pdev;
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int gpmc_cs;
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unsigned long phys_base;
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unsigned int mem_size;
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int gpio_irq;
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struct gpio_desc *int_gpiod;
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struct mtd_info mtd;
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struct onenand_chip onenand;
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struct completion irq_done;
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struct completion dma_done;
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struct dma_chan *dma_chan;
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int freq;
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int (*setup)(void __iomem *base, int *freq_ptr);
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};
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static void omap2_onenand_dma_complete_func(void *completion)
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@ -84,6 +82,65 @@ static inline void write_reg(struct omap2_onenand *c, unsigned short value,
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writew(value, c->onenand.base + reg);
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}
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static int omap2_onenand_set_cfg(struct omap2_onenand *c,
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bool sr, bool sw,
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int latency, int burst_len)
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{
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unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
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reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
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switch (burst_len) {
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case 0: /* continuous */
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break;
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case 4:
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reg |= ONENAND_SYS_CFG1_BL_4;
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break;
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case 8:
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reg |= ONENAND_SYS_CFG1_BL_8;
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break;
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case 16:
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reg |= ONENAND_SYS_CFG1_BL_16;
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break;
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case 32:
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reg |= ONENAND_SYS_CFG1_BL_32;
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break;
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default:
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return -EINVAL;
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}
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if (latency > 5)
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reg |= ONENAND_SYS_CFG1_HF;
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if (latency > 7)
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reg |= ONENAND_SYS_CFG1_VHF;
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if (sr)
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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if (sw)
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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write_reg(c, reg, ONENAND_REG_SYS_CFG1);
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return 0;
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}
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static int omap2_onenand_get_freq(int ver)
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{
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switch ((ver >> 4) & 0xf) {
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case 0:
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return 40;
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case 1:
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return 54;
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case 2:
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return 66;
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case 3:
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return 83;
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case 4:
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return 104;
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}
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return -EINVAL;
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}
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static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
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{
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printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
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@ -152,12 +209,12 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
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}
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reinit_completion(&c->irq_done);
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result = gpio_get_value(c->gpio_irq);
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result = gpiod_get_value(c->int_gpiod);
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if (result < 0) {
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
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intr = read_reg(c, ONENAND_REG_INTERRUPT);
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wait_err("gpio error", state, ctrl, intr);
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return -EIO;
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return result;
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} else if (result == 0) {
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int retry_cnt = 0;
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retry:
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@ -431,8 +488,6 @@ out_copy:
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return 0;
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}
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static struct platform_driver omap2_onenand_driver;
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static void omap2_onenand_shutdown(struct platform_device *pdev)
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{
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struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
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@ -446,105 +501,117 @@ static void omap2_onenand_shutdown(struct platform_device *pdev)
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static int omap2_onenand_probe(struct platform_device *pdev)
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{
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u32 val;
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dma_cap_mask_t mask;
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struct omap_onenand_platform_data *pdata;
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struct omap2_onenand *c;
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struct onenand_chip *this;
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int r;
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int freq, latency, r;
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struct resource *res;
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struct omap2_onenand *c;
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struct gpmc_onenand_info info;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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pdata = dev_get_platdata(&pdev->dev);
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if (pdata == NULL) {
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dev_err(&pdev->dev, "platform data missing\n");
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "error getting memory resource\n");
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return -EINVAL;
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}
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c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
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r = of_property_read_u32(np, "reg", &val);
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if (r) {
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dev_err(dev, "reg not found in DT\n");
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return r;
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}
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c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
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if (!c)
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return -ENOMEM;
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init_completion(&c->irq_done);
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init_completion(&c->dma_done);
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c->gpmc_cs = pdata->cs;
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c->gpio_irq = pdata->gpio_irq;
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if (pdata->dma_channel < 0) {
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/* if -1, don't use DMA */
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c->gpio_irq = 0;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res == NULL) {
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r = -EINVAL;
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dev_err(&pdev->dev, "error getting memory resource\n");
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goto err_kfree;
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}
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c->gpmc_cs = val;
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c->phys_base = res->start;
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c->mem_size = resource_size(res);
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if (request_mem_region(c->phys_base, c->mem_size,
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pdev->dev.driver->name) == NULL) {
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dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
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c->phys_base, c->mem_size);
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r = -EBUSY;
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goto err_kfree;
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}
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c->onenand.base = ioremap(c->phys_base, c->mem_size);
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if (c->onenand.base == NULL) {
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r = -ENOMEM;
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goto err_release_mem_region;
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c->onenand.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(c->onenand.base)) {
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dev_err(dev, "Cannot reserve memory region at 0x%08x, size: 0x%x\n",
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res->start, resource_size(res));
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return PTR_ERR(c->onenand.base);
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}
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if (pdata->onenand_setup != NULL) {
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r = pdata->onenand_setup(c->onenand.base, &c->freq);
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if (r < 0) {
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dev_err(&pdev->dev, "Onenand platform setup failed: "
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"%d\n", r);
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goto err_iounmap;
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}
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c->setup = pdata->onenand_setup;
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c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
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if (IS_ERR(c->int_gpiod)) {
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r = PTR_ERR(c->int_gpiod);
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/* Just try again if this happens */
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if (r != -EPROBE_DEFER)
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dev_err(dev, "error getting gpio: %d\n", r);
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return r;
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}
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if (c->gpio_irq) {
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if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
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||||
dev_err(&pdev->dev, "Failed to request GPIO%d for "
|
||||
"OneNAND\n", c->gpio_irq);
|
||||
goto err_iounmap;
|
||||
}
|
||||
gpio_direction_input(c->gpio_irq);
|
||||
if (c->int_gpiod) {
|
||||
r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
|
||||
omap2_onenand_interrupt,
|
||||
IRQF_TRIGGER_RISING, "onenand", c);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if ((r = request_irq(gpio_to_irq(c->gpio_irq),
|
||||
omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
|
||||
pdev->dev.driver->name, c)) < 0)
|
||||
goto err_release_gpio;
|
||||
|
||||
this->wait = omap2_onenand_wait;
|
||||
c->onenand.wait = omap2_onenand_wait;
|
||||
}
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_MEMCPY, mask);
|
||||
|
||||
c->dma_chan = dma_request_channel(mask, NULL, NULL);
|
||||
|
||||
dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
|
||||
"base %p, freq %d MHz, %s mode\n", c->gpmc_cs, c->phys_base,
|
||||
c->onenand.base, c->freq, c->dma_chan ? "DMA" : "PIO");
|
||||
if (c->dma_chan) {
|
||||
c->onenand.read_bufferram = omap2_onenand_read_bufferram;
|
||||
c->onenand.write_bufferram = omap2_onenand_write_bufferram;
|
||||
}
|
||||
|
||||
c->pdev = pdev;
|
||||
c->mtd.priv = &c->onenand;
|
||||
c->mtd.dev.parent = dev;
|
||||
mtd_set_of_node(&c->mtd, dev->of_node);
|
||||
|
||||
c->mtd.dev.parent = &pdev->dev;
|
||||
mtd_set_of_node(&c->mtd, pdata->of_node);
|
||||
|
||||
this = &c->onenand;
|
||||
if (c->dma_chan) {
|
||||
this->read_bufferram = omap2_onenand_read_bufferram;
|
||||
this->write_bufferram = omap2_onenand_write_bufferram;
|
||||
}
|
||||
dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
|
||||
c->gpmc_cs, c->phys_base, c->onenand.base,
|
||||
c->dma_chan ? "DMA" : "PIO");
|
||||
|
||||
if ((r = onenand_scan(&c->mtd, 1)) < 0)
|
||||
goto err_release_dma;
|
||||
|
||||
freq = omap2_onenand_get_freq(c->onenand.version_id);
|
||||
if (freq > 0) {
|
||||
switch (freq) {
|
||||
case 104:
|
||||
latency = 7;
|
||||
break;
|
||||
case 83:
|
||||
latency = 6;
|
||||
break;
|
||||
case 66:
|
||||
latency = 5;
|
||||
break;
|
||||
case 56:
|
||||
latency = 4;
|
||||
break;
|
||||
default: /* 40 MHz or lower */
|
||||
latency = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
|
||||
freq, latency, &info);
|
||||
if (r)
|
||||
goto err_release_onenand;
|
||||
|
||||
r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
|
||||
latency, info.burst_len);
|
||||
if (r)
|
||||
goto err_release_onenand;
|
||||
|
||||
if (info.sync_read || info.sync_write)
|
||||
dev_info(dev, "optimized timings for %d MHz\n", freq);
|
||||
}
|
||||
|
||||
r = mtd_device_register(&c->mtd, NULL, 0);
|
||||
if (r)
|
||||
goto err_release_onenand;
|
||||
|
|
@ -558,17 +625,6 @@ err_release_onenand:
|
|||
err_release_dma:
|
||||
if (c->dma_chan)
|
||||
dma_release_channel(c->dma_chan);
|
||||
if (c->gpio_irq)
|
||||
free_irq(gpio_to_irq(c->gpio_irq), c);
|
||||
err_release_gpio:
|
||||
if (c->gpio_irq)
|
||||
gpio_free(c->gpio_irq);
|
||||
err_iounmap:
|
||||
iounmap(c->onenand.base);
|
||||
err_release_mem_region:
|
||||
release_mem_region(c->phys_base, c->mem_size);
|
||||
err_kfree:
|
||||
kfree(c);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -581,23 +637,23 @@ static int omap2_onenand_remove(struct platform_device *pdev)
|
|||
if (c->dma_chan)
|
||||
dma_release_channel(c->dma_chan);
|
||||
omap2_onenand_shutdown(pdev);
|
||||
if (c->gpio_irq) {
|
||||
free_irq(gpio_to_irq(c->gpio_irq), c);
|
||||
gpio_free(c->gpio_irq);
|
||||
}
|
||||
iounmap(c->onenand.base);
|
||||
release_mem_region(c->phys_base, c->mem_size);
|
||||
kfree(c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id omap2_onenand_id_table[] = {
|
||||
{ .compatible = "ti,omap2-onenand", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
|
||||
|
||||
static struct platform_driver omap2_onenand_driver = {
|
||||
.probe = omap2_onenand_probe,
|
||||
.remove = omap2_onenand_remove,
|
||||
.shutdown = omap2_onenand_shutdown,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = omap2_onenand_id_table,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,15 +25,43 @@ struct gpmc_nand_ops {
|
|||
|
||||
struct gpmc_nand_regs;
|
||||
|
||||
struct gpmc_onenand_info {
|
||||
bool sync_read;
|
||||
bool sync_write;
|
||||
int burst_len;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_OMAP_GPMC)
|
||||
struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
|
||||
int cs);
|
||||
/**
|
||||
* gpmc_omap_onenand_set_timings - set optimized sync timings.
|
||||
* @cs: Chip Select Region
|
||||
* @freq: Chip frequency
|
||||
* @latency: Burst latency cycle count
|
||||
* @info: Structure describing parameters used
|
||||
*
|
||||
* Sets optimized timings for the @cs region based on @freq and @latency.
|
||||
* Updates the @info structure based on the GPMC settings.
|
||||
*/
|
||||
int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
|
||||
int latency,
|
||||
struct gpmc_onenand_info *info);
|
||||
|
||||
#else
|
||||
static inline struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *regs,
|
||||
int cs)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline
|
||||
int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
|
||||
int latency,
|
||||
struct gpmc_onenand_info *info)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif /* CONFIG_OMAP_GPMC */
|
||||
|
||||
extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
|
||||
|
|
|
|||
Loading…
Reference in New Issue