drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the existing PV_VERT* block and indented it, instead of copy and pasting it first. Without this, changing resolution never worked. Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -212,6 +212,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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PV_HORZB_HFP) |
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VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB,
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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PV_VERTB_VFP) |
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VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
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