gpio: thunderx: Switch to GPIOLIB_IRQCHIP
Use the new infrastructure for hierarchical irqchips in gpiolib. The major part of the rewrite was dues to the fact that the driver was passing around a per-irq pointer to struct thunderx_line * data container, and the central handlers will assume struct gpio_chip * to be passed to we need to use the hwirq as index to look up the struct thunderx_line * for each IRQ. The pushing and pop:ing of the irqdomain was confusing because I've never seen this before, but I tried to replicate it as best I could. I have no chance to test or debug this so I need help. Cc: David Daney <david.daney@cavium.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Brian Masney <masneyb@onstation.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190808123242.5359-4-linus.walleij@linaro.orgalistair/sunxi64-5.4-dsi
Linus Walleij
parent
821c76c4c3
commit
a7fc89f9d5
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@ -539,6 +539,7 @@ config GPIO_THUNDERX
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tristate "Cavium ThunderX/OCTEON-TX GPIO"
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depends on ARCH_THUNDER || (64BIT && COMPILE_TEST)
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depends on PCI_MSI
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select GPIOLIB_IRQCHIP
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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help
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@ -53,7 +53,6 @@ struct thunderx_line {
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struct thunderx_gpio {
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struct gpio_chip chip;
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u8 __iomem *register_base;
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struct irq_domain *irqd;
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struct msix_entry *msix_entries; /* per line MSI-X */
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struct thunderx_line *line_entries; /* per line irq info */
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raw_spinlock_t lock;
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@ -283,54 +282,60 @@ static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
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}
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}
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static void thunderx_gpio_irq_ack(struct irq_data *data)
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static void thunderx_gpio_irq_ack(struct irq_data *d)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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writeq(GPIO_INTR_INTR,
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txline->txgpio->register_base + intr_reg(txline->line));
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txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
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}
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static void thunderx_gpio_irq_mask(struct irq_data *data)
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static void thunderx_gpio_irq_mask(struct irq_data *d)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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writeq(GPIO_INTR_ENA_W1C,
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txline->txgpio->register_base + intr_reg(txline->line));
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txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
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}
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static void thunderx_gpio_irq_mask_ack(struct irq_data *data)
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static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
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txline->txgpio->register_base + intr_reg(txline->line));
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txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
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}
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static void thunderx_gpio_irq_unmask(struct irq_data *data)
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static void thunderx_gpio_irq_unmask(struct irq_data *d)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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writeq(GPIO_INTR_ENA_W1S,
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txline->txgpio->register_base + intr_reg(txline->line));
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txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
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}
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static int thunderx_gpio_irq_set_type(struct irq_data *data,
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static int thunderx_gpio_irq_set_type(struct irq_data *d,
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unsigned int flow_type)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct thunderx_gpio *txgpio = txline->txgpio;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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struct thunderx_line *txline =
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&txgpio->line_entries[irqd_to_hwirq(d)];
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u64 bit_cfg;
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irqd_set_trigger_type(data, flow_type);
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irqd_set_trigger_type(d, flow_type);
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bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
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if (flow_type & IRQ_TYPE_EDGE_BOTH) {
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irq_set_handler_locked(data, handle_fasteoi_ack_irq);
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irq_set_handler_locked(d, handle_fasteoi_ack_irq);
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bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
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} else {
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irq_set_handler_locked(data, handle_fasteoi_mask_irq);
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irq_set_handler_locked(d, handle_fasteoi_mask_irq);
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}
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raw_spin_lock(&txgpio->lock);
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@ -359,33 +364,6 @@ static void thunderx_gpio_irq_disable(struct irq_data *data)
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irq_chip_disable_parent(data);
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}
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static int thunderx_gpio_irq_request_resources(struct irq_data *data)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct thunderx_gpio *txgpio = txline->txgpio;
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int r;
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r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
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if (r)
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return r;
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r = irq_chip_request_resources_parent(data);
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if (r)
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gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
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return r;
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}
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static void thunderx_gpio_irq_release_resources(struct irq_data *data)
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct thunderx_gpio *txgpio = txline->txgpio;
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irq_chip_release_resources_parent(data);
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gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
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}
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/*
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* Interrupts are chained from underlying MSI-X vectors. We have
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* these irq_chip functions to be able to handle level triggering
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@ -402,50 +380,24 @@ static struct irq_chip thunderx_gpio_irq_chip = {
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.irq_unmask = thunderx_gpio_irq_unmask,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_request_resources = thunderx_gpio_irq_request_resources,
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.irq_release_resources = thunderx_gpio_irq_release_resources,
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.irq_set_type = thunderx_gpio_irq_set_type,
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.flags = IRQCHIP_SET_TYPE_MASKED
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};
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static int thunderx_gpio_irq_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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irq_hw_number_t *hwirq,
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unsigned int *type)
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static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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unsigned int child,
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unsigned int child_type,
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unsigned int *parent,
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unsigned int *parent_type)
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{
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struct thunderx_gpio *txgpio = d->host_data;
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struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
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if (WARN_ON(fwspec->param_count < 2))
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return -EINVAL;
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if (fwspec->param[0] >= txgpio->chip.ngpio)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
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*parent = txgpio->base_msi + (2 * child);
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*parent_type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct thunderx_line *txline = arg;
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return irq_domain_set_hwirq_and_chip(d, virq, txline->line,
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&thunderx_gpio_irq_chip, txline);
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}
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static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
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.alloc = thunderx_gpio_irq_alloc,
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.translate = thunderx_gpio_irq_translate
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};
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static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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{
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struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
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return irq_find_mapping(txgpio->irqd, offset);
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}
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static int thunderx_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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@ -453,6 +405,7 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
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struct device *dev = &pdev->dev;
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struct thunderx_gpio *txgpio;
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struct gpio_chip *chip;
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struct gpio_irq_chip *girq;
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int ngpio, i;
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int err = 0;
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@ -497,8 +450,8 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
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}
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txgpio->msix_entries = devm_kcalloc(dev,
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ngpio, sizeof(struct msix_entry),
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GFP_KERNEL);
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ngpio, sizeof(struct msix_entry),
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GFP_KERNEL);
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if (!txgpio->msix_entries) {
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err = -ENOMEM;
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goto out;
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@ -539,27 +492,6 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
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if (err < 0)
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goto out;
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/*
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* Push GPIO specific irqdomain on hierarchy created as a side
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* effect of the pci_enable_msix()
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*/
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txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain,
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0, 0, of_node_to_fwnode(dev->of_node),
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&thunderx_gpio_irqd_ops, txgpio);
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if (!txgpio->irqd) {
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err = -ENOMEM;
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goto out;
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}
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/* Push on irq_data and the domain for each line. */
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for (i = 0; i < ngpio; i++) {
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err = irq_domain_push_irq(txgpio->irqd,
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txgpio->msix_entries[i].vector,
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&txgpio->line_entries[i]);
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if (err < 0)
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dev_err(dev, "irq_domain_push_irq: %d\n", err);
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}
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chip->label = KBUILD_MODNAME;
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chip->parent = dev;
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chip->owner = THIS_MODULE;
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@ -574,11 +506,28 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
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chip->set = thunderx_gpio_set;
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chip->set_multiple = thunderx_gpio_set_multiple;
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chip->set_config = thunderx_gpio_set_config;
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chip->to_irq = thunderx_gpio_to_irq;
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girq = &chip->irq;
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girq->chip = &thunderx_gpio_irq_chip;
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girq->fwnode = of_node_to_fwnode(dev->of_node);
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girq->parent_domain =
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irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
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girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
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girq->handler = handle_bad_irq;
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girq->default_type = IRQ_TYPE_NONE;
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err = devm_gpiochip_add_data(dev, chip, txgpio);
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if (err)
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goto out;
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/* Push on irq_data and the domain for each line. */
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for (i = 0; i < ngpio; i++) {
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err = irq_domain_push_irq(chip->irq.domain,
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txgpio->msix_entries[i].vector,
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chip);
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if (err < 0)
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dev_err(dev, "irq_domain_push_irq: %d\n", err);
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}
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dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
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ngpio, chip->base);
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return 0;
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@ -593,10 +542,10 @@ static void thunderx_gpio_remove(struct pci_dev *pdev)
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struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
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for (i = 0; i < txgpio->chip.ngpio; i++)
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irq_domain_pop_irq(txgpio->irqd,
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irq_domain_pop_irq(txgpio->chip.irq.domain,
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txgpio->msix_entries[i].vector);
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irq_domain_remove(txgpio->irqd);
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irq_domain_remove(txgpio->chip.irq.domain);
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pci_set_drvdata(pdev, NULL);
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}
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