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Adds support getting the divider registers for the MAIN PLL that was once 

thought to be hidden.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJTcQUFAAoJEBmUBAuBoyj0hFkP/2lSyq+o4swmhovXFV8xLlvg
 lgIq7m7RXqc8kSbz7RhbVOmjvTr7Kb5YRBQO7mIqJQpM/4lzUrsgGc9m7LZc6Rnh
 eP4Dt37gHCmacEwtjRp5nvQ5t0NaXXocctyb0LHKjuDRJlNkqd6Qcx+Lj4fXjsCf
 flWAxJN2ZG5BA8m5KCWPemYjiQblQUKNphphjte1AWgvl/yyzOSLneobnfdMFbiR
 jkaUBAw2vUYvz4NjJzw9f1aS8EUpc2IO6tLXERVZ7V6+rCakHK+DH1tzstlfqES0
 zIdEzoV1PzBiIreptLGH9EbM8nmFIX/7whijtEvOoxkHeLPtTUnTm0Mv0KGVR5wF
 k3tMPeNP0BDNJ/69nPnxbr7dSw1xkLU9UavY+/t7Jq5fAt4/DsOoPxRnbxOQI+SM
 Lf3KS+j7nLQ7ueOgaB7tiDS5unNRqaY0ys0MggeA9xA544gcTf/2sg/qS9ur7PP5
 jJ0yumtyunDCCI2xh0vUOipHNb0wbx9gCylgvPzatB8kDYaInOLA+ifVo9GJECd4
 jdKoS848wBYZESSaiEGGL5VcLhKAhE4ycLpsWHh5wFScr+4KfBVr/vcm2cZs3XIG
 ISANaRoDFOtk8jCwNw2wTveW1tLsQHFU1ldoMfFcvKzESQkoe4PM+s4waRLduPLx
 3OjACqD98ydI76tNli0f
 =anDE
 -----END PGP SIGNATURE-----

Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga

Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.
hifive-unleashed-5.1
Mike Turquette 2014-05-12 19:11:13 -07:00
parent b4b3bfd0b3 0691bb1b5a
commit a854aea24c
3 changed files with 23 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/socfpga/clk-gate.c
View File

@ -32,7 +32,6 @@
#define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
#define div_mask(width) ((1 << (width)) - 1)
#define streq(a, b) (strcmp((a), (b)) == 0)
#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)

22
drivers/clk/socfpga/clk-periph.c
View File

@ -29,12 +29,18 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
u32 div;
u32 div, val;
if (socfpgaclk->fixed_div)
if (socfpgaclk->fixed_div) {
div = socfpgaclk->fixed_div;
else
} else {
if (socfpgaclk->div_reg) {
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= div_mask(socfpgaclk->width);
parent_rate /= (val + 1);
}
div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
}
return parent_rate / div;
}
@ -54,6 +60,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
struct clk_init_data init;
int rc;
u32 fixed_div;
u32 div_reg[3];
of_property_read_u32(node, "reg", &reg);
@ -63,6 +70,15 @@ static __init void __socfpga_periph_init(struct device_node *node,
periph_clk->hw.reg = clk_mgr_base_addr + reg;
rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
if (!rc) {
periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
periph_clk->shift = div_reg[1];
periph_clk->width = div_reg[2];
} else {
periph_clk->div_reg = 0;
}
rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
if (rc)
periph_clk->fixed_div = 0;

4
drivers/clk/socfpga/clk.h
View File

@ -27,6 +27,7 @@
#define CLKMGR_PERPLL_SRC 0xAC
#define SOCFPGA_MAX_PARENTS 3
#define div_mask(width) ((1 << (width)) - 1)
extern void __iomem *clk_mgr_base_addr;
@ -52,6 +53,9 @@ struct socfpga_periph_clk {
struct clk_gate hw;
char *parent_name;
u32 fixed_div;
void __iomem *div_reg;
u32 width; /* only valid if div_reg != 0 */
u32 shift; /* only valid if div_reg != 0 */
};
#endif /* SOCFPGA_CLK_H */