drm/i915/guc: Wait for ucode DMA transfer completion
We silently assumed that DMA transfer will be completed within assumed timeout and thus we were waiting only at last step for GuC to become ready. Add intermediate wait to catch unexpected delays in DMA transfer. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171103151816.62048-2-michal.wajdeczko@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
2ceddb1893
commit
a86af2314a
|
@ -160,6 +160,8 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
|
|||
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
||||
struct intel_uc_fw *guc_fw = &guc->fw;
|
||||
unsigned long offset;
|
||||
u32 status;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* The header plus uCode will be copied to WOPCM via DMA, excluding any
|
||||
|
@ -182,7 +184,12 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
|
|||
/* Finally start the DMA */
|
||||
I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
|
||||
|
||||
return 0;
|
||||
/* Wait for DMA to finish */
|
||||
ret = __intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,
|
||||
2, 100, &status);
|
||||
DRM_DEBUG_DRIVER("GuC DMA status %#x\n", status);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
Loading…
Reference in a new issue