arm: omap: irq: remove rest of irq_banks usage
now we can finally remove the pointless irq_banks array. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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421b090c83
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a88ab43083
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@ -49,8 +49,8 @@
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#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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#define INTCPS_NR_ILR_REGS 128
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#define INTCPS_NR_MIR_REGS 3
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#define INTCPS_NR_IRQS 96
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/*
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* OMAP2 has a number of different interrupt controllers, each interrupt
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@ -58,15 +58,6 @@
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* fairly consistent for each bank, but not all registers are implemented
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* for each bank.. when in doubt, consult the TRM.
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*/
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static struct omap_irq_bank {
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void __iomem *base_reg;
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unsigned int nr_irqs;
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} __attribute__ ((aligned(4))) irq_banks[] = {
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{
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/* MPU INTC */
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.nr_irqs = 96,
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},
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};
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static struct irq_domain *domain;
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static void __iomem *omap_irq_base;
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@ -78,7 +69,7 @@ struct omap3_intc_regs {
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u32 protection;
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u32 idle;
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u32 threshold;
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u32 ilr[INTCPS_NR_IRQS];
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u32 ilr[INTCPS_NR_ILR_REGS];
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u32 mir[INTCPS_NR_MIR_REGS];
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};
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@ -105,13 +96,14 @@ static void omap_mask_ack_irq(struct irq_data *d)
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omap_ack_irq(d);
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}
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static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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static void __init omap_irq_soft_reset(void)
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{
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unsigned long tmp;
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tmp = intc_readl(INTC_REVISION) & 0xff;
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pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
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bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
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omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
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tmp = intc_readl(INTC_SYSCONFIG);
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tmp |= 1 << 1; /* soft reset */
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@ -126,17 +118,12 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
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int omap_irq_pending(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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int irq;
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for (irq = 0; irq < bank->nr_irqs; irq += 32)
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for (irq = 0; irq < omap_nr_irqs; irq += 32)
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if (intc_readl(INTC_PENDING_IRQ0 +
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((irq >> 5) << 5)))
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return 1;
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}
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return 0;
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}
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@ -163,9 +150,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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static void __init omap_init_irq(u32 base, int nr_irqs,
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struct device_node *node)
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{
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unsigned long nr_of_irqs = 0;
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unsigned int nr_banks = 0;
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int i, j, irq_base;
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int j, irq_base;
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omap_irq_base = ioremap(base, SZ_4K);
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if (WARN_ON(!omap_irq_base))
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@ -182,29 +167,10 @@ static void __init omap_init_irq(u32 base, int nr_irqs,
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domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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omap_irq_soft_reset();
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bank->nr_irqs = nr_irqs;
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/* Static mapping, never released */
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bank->base_reg = ioremap(base, SZ_4K);
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if (!bank->base_reg) {
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pr_err("Could not ioremap irq bank%i\n", i);
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continue;
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}
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omap_irq_bank_init_one(bank);
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for (j = 0; j < bank->nr_irqs; j += 32)
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omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
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nr_of_irqs += bank->nr_irqs;
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nr_banks++;
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}
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pr_info("Total of %ld interrupts on %d active controller%s\n",
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nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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for (j = 0; j < omap_nr_irqs; j += 32)
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omap_alloc_gc(omap_irq_base + j, j + irq_base, 32);
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}
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void __init omap2_init_irq(void)
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@ -303,45 +269,45 @@ void __init omap_intc_of_init(void)
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}
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
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static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
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static struct omap3_intc_regs intc_context;
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void omap_intc_save_context(void)
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{
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int ind = 0, i = 0;
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for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
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intc_context[ind].sysconfig =
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int i;
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intc_context.sysconfig =
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intc_readl(INTC_SYSCONFIG);
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intc_context[ind].protection =
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intc_context.protection =
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intc_readl(INTC_PROTECTION);
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intc_context[ind].idle =
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intc_context.idle =
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intc_readl(INTC_IDLE);
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intc_context[ind].threshold =
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intc_context.threshold =
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intc_readl(INTC_THRESHOLD);
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for (i = 0; i < INTCPS_NR_IRQS; i++)
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intc_context[ind].ilr[i] =
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for (i = 0; i < omap_nr_irqs; i++)
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intc_context.ilr[i] =
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intc_readl((INTC_ILR0 + 0x4 * i));
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_context[ind].mir[i] =
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intc_context.mir[i] =
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intc_readl(INTC_MIR0 + (0x20 * i));
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}
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}
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void omap_intc_restore_context(void)
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{
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int ind = 0, i = 0;
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int i;
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for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
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intc_writel(INTC_SYSCONFIG, intc_context[ind].sysconfig);
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intc_writel(INTC_PROTECTION, intc_context[ind].protection);
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intc_writel(INTC_IDLE, intc_context[ind].idle);
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intc_writel(INTC_THRESHOLD, intc_context[ind].threshold);
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for (i = 0; i < INTCPS_NR_IRQS; i++)
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intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
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intc_writel(INTC_PROTECTION, intc_context.protection);
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intc_writel(INTC_IDLE, intc_context.idle);
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intc_writel(INTC_THRESHOLD, intc_context.threshold);
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for (i = 0; i < omap_nr_irqs; i++)
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intc_writel(INTC_ILR0 + 0x4 * i,
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intc_context[ind].ilr[i]);
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intc_context.ilr[i]);
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for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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intc_writel(INTC_MIR0 + 0x20 * i,
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intc_context[ind].mir[i]);
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}
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intc_context.mir[i]);
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/* MIRs are saved and restore with other PRCM registers */
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}
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