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ARM: dts: arm: Fix SP805 clocks 

The SP805 binding sets the name for the actual watchdog clock to
"wdog_clk" (with an underscore).

Change the name in the DTs for ARM Ltd. platforms to match that. The
Linux and U-Boot driver use the *first* clock for this purpose anyway,
so it does not break anything.

For MPS2 we only specify one clock so far, but the binding requires
two clocks to be named.

In practice, Linux would pick a clock named "apb_pclk" for the bus
clock, and the Linux and U-Boot SP805 driver would use the first clock
to derive the actual watchdog counter frequency. So since currently both
are the very same clock, we can just double the clock reference, and add
the correct clock-names, to match the binding.

Link: https://lore.kernel.org/r/20200828130602.42203-8-andre.przywara@arm.com
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
zero-sugar-mainline-defconfig
Andre Przywara 2020-08-28 14:05:59 +01:00 committed by Sudeep Holla
parent 34a4591871
commit a894c6dd56
9 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/arm-realview-eb.dtsi
View File

@ -390,7 +390,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x10010000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};

4
arch/arm/boot/dts/arm-realview-pb11mp.dts
View File

@ -546,7 +546,7 @@
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
@ -556,7 +556,7 @@
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
};
timer01: timer@10011000 {

4
arch/arm/boot/dts/arm-realview-pbx.dtsi
View File

@ -381,7 +381,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x1000f000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
@ -389,7 +389,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x10010000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};

4
arch/arm/boot/dts/mps2.dtsi
View File

@ -199,8 +199,8 @@
arm,primecell-periphid = <0x00141805>;
reg = <0x8000 0x1000>;
interrupts = <0>;
clocks = <&sysclk>;
clock-names = "apb_pclk";
clocks = <&sysclk>, <&sysclk>;
clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
};

2
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
View File

@ -280,7 +280,7 @@
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
};
v2m_timer01: timer@110000 {

2
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -198,7 +198,7 @@
reg = <0x0f000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
};
v2m_timer01: timer@11000 {

4
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
View File

@ -87,8 +87,8 @@
status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&sys_pll>;
clock-names = "apb_pclk";
clocks = <&sys_pll>, <&sys_pll>;
clock-names = "wdog_clk", "apb_pclk";
};
gic: interrupt-controller@2c001000 {

2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -128,7 +128,7 @@
reg = <0 0x2a490000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&oscclk6a>, <&oscclk6a>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
};
hdlcd@2b000000 {

2
arch/arm/boot/dts/vexpress-v2p-ca9.dts
View File

@ -132,7 +132,7 @@
reg = <0x100e5000 0x1000>;
interrupts = <0 51 4>;
clocks = <&oscclk2>, <&oscclk2>;
clock-names = "wdogclk", "apb_pclk";
clock-names = "wdog_clk", "apb_pclk";
};
scu@1e000000 {