drm/radeon: properly init UVD MC bits on R600
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -992,6 +992,8 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev)
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WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
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WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
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WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
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@ -1042,6 +1044,8 @@ static void r600_pcie_gart_disable(struct radeon_device *rdev)
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WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
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WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
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radeon_gart_table_vram_unpin(rdev);
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}
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@ -334,7 +334,7 @@
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#define MC_VM_AGP_BOT 0x2188
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#define MC_VM_AGP_BASE 0x218C
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#define MC_VM_FB_LOCATION 0x2180
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#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
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#define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124
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#define ENABLE_L1_TLB (1 << 0)
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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
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#define ENABLE_L1_STRICT_ORDERING (1 << 2)
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@ -354,12 +354,14 @@
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#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
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#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
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#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
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#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
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#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
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#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
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#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
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#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
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#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
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#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
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#define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c
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#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
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#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
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#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
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