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ARM: dts: imx6sl-evk-csi: add new dts file for csi 

add new dts file for csi since csi and epdc has pin conflict

Signed-off-by: Robby Cai <robby.cai@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Robby Cai 2019-09-30 17:31:47 +08:00 committed by Dong Aisheng
parent aad3b65f3a
commit a95001e8f7
3 changed files with 82 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
View File

@ -556,6 +556,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-evk-csi.dtb \
imx6sl-evk-uart.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \

17
arch/arm/boot/dts/imx6sl-evk-csi.dts 100644
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
//
//Copyright (C) 2013 Freescale Semiconductor, Inc.
#include "imx6sl-evk.dts"
&csi {
status = "okay";
};
&i2c3 {
status = "okay";
};
&epdc {
status = "disabled";
};

64
arch/arm/boot/dts/imx6sl-evk.dts
View File

@ -148,6 +148,14 @@
status = "okay";
};
&csi {
port {
csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&ecspi1 {
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
@ -392,6 +400,34 @@
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "disabled";
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_0>;
clocks = <&clks IMX6SL_CLK_CSI>;
clock-names = "csi_mclk";
AVDD-supply = <&vgen6_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio1 25 1>;
rst-gpios = <&gpio1 26 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi_ep>;
};
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@ -510,6 +546,13 @@
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@ -713,6 +756,27 @@
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
pinctrl_csi_0: csigrp-0 {
fsl,pins = <
MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
>;
};
};
};