Rockchip soc-specific driver changes containing support for the
rk3399 powerdomains and necessary infrastructure changes to accomodate them - like supporting nested powerdomains here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJXDJOJAAoJEPOmecmc0R2BUzYH/A8lSeOeH61VnPNuGG+s8KvF yPL7Plz/rVDj5mz+CQPmqdajxS8qDIBqiXKjno/BpOIdQ+5MRJW47wjWlvhFV3rl tde+rnfR7doh2cjDU2W7FVtWEz/vPGzboffgCtXGpm6qs2f6Uj+PK/NWfKjTsbog 1VBk117DbGYVdfamfASTykwV9SZjPgjYBEyppWAPAU9d6Jb73aRbdQfkiCQCvrJg 7JGg5hWwbd9TDVrUs3RZ8+PNMZnVEA3vcxNrvvhtivrAA1mSCl+1H1bTFcKEo+1C 7PmEEBZh6jLEQ+5N2Yftsf8FF9hiB7JwSw/jLPBIM9Isv5MOF5BvZoDlDuo8/5A= =aaLP -----END PGP SIGNATURE----- Merge tag 'v4.7-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/drivers Rockchip soc-specific driver changes containing support for the rk3399 powerdomains and necessary infrastructure changes to accomodate them - like supporting nested powerdomains here. * tag 'v4.7-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: power-domain: check the existing of regmap soc: rockchip: power-domain: Modify power domain driver for rk3399 dt-bindings: add binding for rk3399 power domains dt-bindings: add power-domain header for RK3399 SoCs soc: rockchip: power-domain: add support for sub-power domains soc: rockchip: power-domain: allow domains only handling idle requests soc: rockchip: power-domain: make idle handling optional Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
a961bf24ba
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@ -7,6 +7,7 @@ Required properties for power domain controller:
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- compatible: Should be one of the following.
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"rockchip,rk3288-power-controller" - for RK3288 SoCs.
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"rockchip,rk3368-power-controller" - for RK3368 SoCs.
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"rockchip,rk3399-power-controller" - for RK3399 SoCs.
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- #power-domain-cells: Number of cells in a power-domain specifier.
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Should be 1 for multiple PM domains.
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- #address-cells: Should be 1.
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@ -16,6 +17,7 @@ Required properties for power domain sub nodes:
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- reg: index of the power domain, should use macros in:
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"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
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"include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
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"include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
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- clocks (optional): phandles to clocks which need to be enabled while power domain
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switches state.
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@ -45,12 +47,41 @@ Example:
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};
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};
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Example 2:
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power: power-controller {
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compatible = "rockchip,rk3399-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_vio {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <RK3399_PD_VIO>;
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pd_vo {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <RK3399_PD_VO>;
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pd_vopb {
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reg = <RK3399_PD_VOPB>;
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};
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pd_vopl {
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reg = <RK3399_PD_VOPL>;
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};
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};
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};
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};
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Node of a device using power domains must have a power-domains property,
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containing a phandle to the power device node and an index specifying which
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power domain to use.
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The index should use macros in:
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"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
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"include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
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"include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
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Example of the node using power domain:
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@ -65,3 +96,9 @@ Example of the node using power domain:
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power-domains = <&power RK3368_PD_GPU_1>;
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/* ... */
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};
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node {
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/* ... */
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power-domains = <&power RK3399_PD_VOPB>;
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/* ... */
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};
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@ -19,6 +19,7 @@
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/power/rk3368-power.h>
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#include <dt-bindings/power/rk3399-power.h>
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struct rockchip_domain_info {
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int pwr_mask;
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@ -66,11 +67,11 @@ struct rockchip_pmu {
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#define DOMAIN(pwr, status, req, idle, ack) \
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{ \
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.pwr_mask = BIT(pwr), \
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.status_mask = BIT(status), \
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.req_mask = BIT(req), \
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.idle_mask = BIT(idle), \
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.ack_mask = BIT(ack), \
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.pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
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.status_mask = (status >= 0) ? BIT(status) : 0, \
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.req_mask = (req >= 0) ? BIT(req) : 0, \
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.idle_mask = (idle >= 0) ? BIT(idle) : 0, \
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.ack_mask = (ack >= 0) ? BIT(ack) : 0, \
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}
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#define DOMAIN_RK3288(pwr, status, req) \
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@ -79,6 +80,9 @@ struct rockchip_pmu {
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#define DOMAIN_RK3368(pwr, status, req) \
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DOMAIN(pwr, status, req, (req) + 16, req)
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#define DOMAIN_RK3399(pwr, status, req) \
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DOMAIN(pwr, status, req, req, req)
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static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
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{
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struct rockchip_pmu *pmu = pd->pmu;
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@ -96,6 +100,9 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int val;
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if (pd_info->req_mask == 0)
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return 0;
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regmap_update_bits(pmu->regmap, pmu->info->req_offset,
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pd_info->req_mask, idle ? -1U : 0);
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@ -116,6 +123,10 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
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struct rockchip_pmu *pmu = pd->pmu;
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unsigned int val;
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/* check idle status for idle-only domains */
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if (pd->info->status_mask == 0)
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return !rockchip_pmu_domain_is_idle(pd);
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regmap_read(pmu->regmap, pmu->info->status_offset, &val);
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/* 1'b0: power on, 1'b1: power off */
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@ -127,6 +138,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
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{
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struct rockchip_pmu *pmu = pd->pmu;
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if (pd->info->pwr_mask == 0)
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return;
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regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
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pd->info->pwr_mask, on ? 0 : -1U);
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@ -360,6 +374,61 @@ static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
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regmap_write(pmu->regmap, domain_reg_offset + 4, count);
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}
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static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
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struct device_node *parent)
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{
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struct device_node *np;
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struct generic_pm_domain *child_domain, *parent_domain;
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int error;
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for_each_child_of_node(parent, np) {
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u32 idx;
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error = of_property_read_u32(parent, "reg", &idx);
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if (error) {
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dev_err(pmu->dev,
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"%s: failed to retrieve domain id (reg): %d\n",
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parent->name, error);
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goto err_out;
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}
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parent_domain = pmu->genpd_data.domains[idx];
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error = rockchip_pm_add_one_domain(pmu, np);
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if (error) {
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dev_err(pmu->dev, "failed to handle node %s: %d\n",
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np->name, error);
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goto err_out;
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}
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error = of_property_read_u32(np, "reg", &idx);
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if (error) {
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dev_err(pmu->dev,
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"%s: failed to retrieve domain id (reg): %d\n",
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np->name, error);
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goto err_out;
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}
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child_domain = pmu->genpd_data.domains[idx];
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error = pm_genpd_add_subdomain(parent_domain, child_domain);
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if (error) {
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dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
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parent_domain->name, child_domain->name, error);
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goto err_out;
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} else {
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dev_dbg(pmu->dev, "%s add subdomain: %s\n",
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parent_domain->name, child_domain->name);
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}
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rockchip_pm_add_subdomain(pmu, np);
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}
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return 0;
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err_out:
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of_node_put(np);
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return error;
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}
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static int rockchip_pm_domain_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -406,6 +475,10 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
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}
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pmu->regmap = syscon_node_to_regmap(parent->of_node);
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if (IS_ERR(pmu->regmap)) {
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dev_err(dev, "no regmap available\n");
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return PTR_ERR(pmu->regmap);
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}
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/*
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* Configure power up and down transition delays for CORE
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@ -426,6 +499,14 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
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of_node_put(node);
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goto err_out;
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}
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error = rockchip_pm_add_subdomain(pmu, node);
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if (error < 0) {
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dev_err(dev, "failed to handle subdomain node %s: %d\n",
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node->name, error);
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of_node_put(node);
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goto err_out;
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}
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}
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if (error) {
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@ -457,6 +538,36 @@ static const struct rockchip_domain_info rk3368_pm_domains[] = {
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[RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2),
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};
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static const struct rockchip_domain_info rk3399_pm_domains[] = {
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[RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1),
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[RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1),
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[RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1),
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[RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15),
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[RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16),
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[RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1),
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[RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2),
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[RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14),
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[RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17),
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[RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0),
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[RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3),
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[RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4),
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[RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5),
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[RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6),
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[RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1),
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[RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7),
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[RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8),
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[RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9),
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[RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10),
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[RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11),
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[RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23),
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[RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24),
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[RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12),
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[RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22),
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[RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27),
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[RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28),
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[RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29),
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};
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static const struct rockchip_pmu_info rk3288_pmu = {
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.pwr_offset = 0x08,
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.status_offset = 0x0c,
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@ -491,6 +602,23 @@ static const struct rockchip_pmu_info rk3368_pmu = {
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.domain_info = rk3368_pm_domains,
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};
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static const struct rockchip_pmu_info rk3399_pmu = {
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.pwr_offset = 0x14,
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.status_offset = 0x18,
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.req_offset = 0x60,
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.idle_offset = 0x64,
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.ack_offset = 0x68,
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.core_pwrcnt_offset = 0x9c,
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.gpu_pwrcnt_offset = 0xa4,
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.core_power_transition_time = 24,
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.gpu_power_transition_time = 24,
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.num_domains = ARRAY_SIZE(rk3399_pm_domains),
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.domain_info = rk3399_pm_domains,
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};
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static const struct of_device_id rockchip_pm_domain_dt_match[] = {
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{
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.compatible = "rockchip,rk3288-power-controller",
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@ -500,6 +628,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
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.compatible = "rockchip,rk3368-power-controller",
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.data = (void *)&rk3368_pmu,
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},
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{
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.compatible = "rockchip,rk3399-power-controller",
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.data = (void *)&rk3399_pmu,
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},
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{ /* sentinel */ },
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};
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53
include/dt-bindings/power/rk3399-power.h
Normal file
53
include/dt-bindings/power/rk3399-power.h
Normal file
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@ -0,0 +1,53 @@
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#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
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#define __DT_BINDINGS_POWER_RK3399_POWER_H__
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/* VD_CORE_L */
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#define RK3399_PD_A53_L0 0
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#define RK3399_PD_A53_L1 1
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#define RK3399_PD_A53_L2 2
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#define RK3399_PD_A53_L3 3
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#define RK3399_PD_SCU_L 4
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/* VD_CORE_B */
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#define RK3399_PD_A72_B0 5
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#define RK3399_PD_A72_B1 6
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#define RK3399_PD_SCU_B 7
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/* VD_LOGIC */
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#define RK3399_PD_TCPD0 8
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#define RK3399_PD_TCPD1 9
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#define RK3399_PD_CCI 10
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#define RK3399_PD_CCI0 11
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#define RK3399_PD_CCI1 12
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#define RK3399_PD_PERILP 13
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#define RK3399_PD_PERIHP 14
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#define RK3399_PD_VIO 15
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#define RK3399_PD_VO 16
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#define RK3399_PD_VOPB 17
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#define RK3399_PD_VOPL 18
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#define RK3399_PD_ISP0 19
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#define RK3399_PD_ISP1 20
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#define RK3399_PD_HDCP 21
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#define RK3399_PD_GMAC 22
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#define RK3399_PD_EMMC 23
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#define RK3399_PD_USB3 24
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#define RK3399_PD_EDP 25
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#define RK3399_PD_GIC 26
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#define RK3399_PD_SD 27
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#define RK3399_PD_SDIOAUDIO 28
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#define RK3399_PD_ALIVE 29
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/* VD_CENTER */
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#define RK3399_PD_CENTER 30
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#define RK3399_PD_VCODEC 31
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#define RK3399_PD_VDU 32
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#define RK3399_PD_RGA 33
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#define RK3399_PD_IEP 34
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/* VD_GPU */
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#define RK3399_PD_GPU 35
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/* VD_PMU */
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#define RK3399_PD_PMU 36
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#endif
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