clk: stm32mp1: add Post-dividers for PLL
Each PLL has 3 outputs with post-dividers. pll1_p is dedicated for Cortex-A7 pll1_q is not connected pll1_r is not connected pll2_p is dedicated for AXI pll2_q is dedicated for GPU pll2_r is dedicated for DDR pll3_p is dedicated for mcu pll3_q is for Peripheral Kernel Clock pll3_r is for Peripheral Kernel Clock pll4_p is for Peripheral Kernel Clock pll4_q is for Peripheral Kernel Clock pll4_r is for Peripheral Kernel Clock Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>hifive-unleashed-5.1
Gabriel Fernandez
Michael Turquette
parent
c6cf4d3248
commit
a97703c59f
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@ -166,6 +166,23 @@ struct stm32_gate_cfg {
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const struct clk_ops *ops;
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};
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struct stm32_div_cfg {
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struct div_cfg *div;
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const struct clk_ops *ops;
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};
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struct stm32_mux_cfg {
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struct mux_cfg *mux;
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const struct clk_ops *ops;
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};
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/* STM32 Composite clock */
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struct stm32_composite_cfg {
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const struct stm32_gate_cfg *gate;
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const struct stm32_div_cfg *div;
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const struct stm32_mux_cfg *mux;
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};
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static struct clk_hw *
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_clk_hw_register_gate(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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@ -259,6 +276,51 @@ const struct clk_ops mp1_gate_clk_ops = {
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.is_enabled = clk_gate_is_enabled,
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};
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static struct clk_hw *_get_stm32_mux(void __iomem *base,
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const struct stm32_mux_cfg *cfg,
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spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk_hw *mux_hw;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->reg = cfg->mux->reg_off + base;
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mux->shift = cfg->mux->shift;
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mux->mask = (1 << cfg->mux->width) - 1;
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mux->flags = cfg->mux->mux_flags;
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mux->table = cfg->mux->table;
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mux->lock = lock;
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mux_hw = &mux->hw;
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return mux_hw;
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}
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static struct clk_hw *_get_stm32_div(void __iomem *base,
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const struct stm32_div_cfg *cfg,
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spinlock_t *lock)
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{
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struct clk_divider *div;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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div->reg = cfg->div->reg_off + base;
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div->shift = cfg->div->shift;
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div->width = cfg->div->width;
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div->flags = cfg->div->div_flags;
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div->table = cfg->div->table;
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div->lock = lock;
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return &div->hw;
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}
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static struct clk_hw *
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_get_stm32_gate(void __iomem *base,
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const struct stm32_gate_cfg *cfg, spinlock_t *lock)
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@ -322,6 +384,61 @@ clk_stm32_register_gate_ops(struct device *dev,
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return hw;
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}
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static struct clk_hw *
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clk_stm32_register_composite(struct device *dev,
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const char *name, const char * const *parent_names,
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int num_parents, void __iomem *base,
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const struct stm32_composite_cfg *cfg,
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unsigned long flags, spinlock_t *lock)
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{
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const struct clk_ops *mux_ops, *div_ops, *gate_ops;
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struct clk_hw *mux_hw, *div_hw, *gate_hw;
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mux_hw = NULL;
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div_hw = NULL;
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gate_hw = NULL;
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mux_ops = NULL;
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div_ops = NULL;
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gate_ops = NULL;
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if (cfg->mux) {
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mux_hw = _get_stm32_mux(base, cfg->mux, lock);
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if (!IS_ERR(mux_hw)) {
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mux_ops = &clk_mux_ops;
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if (cfg->mux->ops)
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mux_ops = cfg->mux->ops;
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}
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}
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if (cfg->div) {
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div_hw = _get_stm32_div(base, cfg->div, lock);
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if (!IS_ERR(div_hw)) {
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div_ops = &clk_divider_ops;
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if (cfg->div->ops)
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div_ops = cfg->div->ops;
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}
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}
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if (cfg->gate) {
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gate_hw = _get_stm32_gate(base, cfg->gate, lock);
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if (!IS_ERR(gate_hw)) {
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gate_ops = &clk_gate_ops;
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if (cfg->gate->ops)
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gate_ops = cfg->gate->ops;
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}
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}
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return clk_hw_register_composite(dev, name, parent_names, num_parents,
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mux_hw, mux_ops, div_hw, div_ops,
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gate_hw, gate_ops, flags);
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}
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/* STM32 PLL */
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struct stm32_pll_obj {
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@ -527,6 +644,17 @@ _clk_stm32_register_gate(struct device *dev,
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lock);
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}
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static struct clk_hw *
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_clk_stm32_register_composite(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
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cfg->num_parents, base, cfg->cfg,
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cfg->flags, lock);
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}
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#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
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{\
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.id = _id,\
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@ -624,6 +752,10 @@ _clk_stm32_register_gate(struct device *dev,
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.ops = _ops,\
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})
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#define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
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_STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
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NULL)\
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#define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
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_STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
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&mp1_gate_clk_ops)\
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@ -632,6 +764,44 @@ _clk_stm32_register_gate(struct device *dev,
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STM32_GATE(_id, _name, _parent, _flags,\
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_GATE_MP1(_offset, _bit_idx, _gate_flags))
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#define _STM32_DIV(_div_offset, _div_shift, _div_width,\
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_div_flags, _div_table, _ops)\
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.div = &(struct stm32_div_cfg) {\
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&(struct div_cfg) {\
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.reg_off = _div_offset,\
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.shift = _div_shift,\
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.width = _div_width,\
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.div_flags = _div_flags,\
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.table = _div_table,\
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},\
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.ops = _ops,\
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}
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#define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
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_STM32_DIV(_div_offset, _div_shift, _div_width,\
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_div_flags, _div_table, NULL)\
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#define PARENT(_parent) ((const char *[]) { _parent})
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#define _NO_MUX .mux = NULL
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#define _NO_DIV .div = NULL
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#define _NO_GATE .gate = NULL
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#define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
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{\
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.id = _id,\
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.name = _name,\
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.parent_names = _parents,\
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.num_parents = ARRAY_SIZE(_parents),\
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.flags = _flags,\
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.cfg = &(struct stm32_composite_cfg) {\
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_gate,\
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_mux,\
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_div,\
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},\
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.func = _clk_stm32_register_composite,\
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}
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static const struct clock_config stm32mp1_clock_cfg[] = {
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/* Oscillator divider */
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DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
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@ -661,6 +831,57 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
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PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
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PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
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/* ODF */
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COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
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_GATE(RCC_PLL1CR, 4, 0),
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_NO_MUX,
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_DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
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COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
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_GATE(RCC_PLL2CR, 4, 0),
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_NO_MUX,
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_DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
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COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
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_GATE(RCC_PLL2CR, 5, 0),
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_NO_MUX,
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_DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
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COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
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_GATE(RCC_PLL2CR, 6, 0),
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_NO_MUX,
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_DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
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COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
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_GATE(RCC_PLL3CR, 4, 0),
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_NO_MUX,
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_DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
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COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
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_GATE(RCC_PLL3CR, 5, 0),
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_NO_MUX,
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_DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
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COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
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_GATE(RCC_PLL3CR, 6, 0),
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_NO_MUX,
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_DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
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COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
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_GATE(RCC_PLL4CR, 4, 0),
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_NO_MUX,
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_DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
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COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
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_GATE(RCC_PLL4CR, 5, 0),
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_NO_MUX,
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_DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
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COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
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_GATE(RCC_PLL4CR, 6, 0),
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_NO_MUX,
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_DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
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};
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struct stm32_clock_match_data {
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